Semiconductor Quantum Structures Using Preferential Tunneling Through Thin Insulator Layers

ABSTRACT

Novel and useful semiconductor structures using preferential tunneling through thin insulator layers. Semiconductor quantum structures are implemented using tunneling through a thin oxide layer. The quantum dots are fabricated with semiconductor wells, 3D fins or combinations thereof, while the tunneling path and any optional quantum transport path is implemented with gate layers. The oxide layer between the gate and the well is thin enough in the nanometer semiconductor processes to permit significant tunneling. Having a thin oxide layer on only one side of the well, while having thick oxide layers on all other sides, results in a preferential tunneling direction where tunneling is restricted to a small area resulting in aperture tunneling. The advantage being constraining quantum transport to a very narrow path, which can be approximated as unidimensional. In alternative embodiments, more than one preferential tunneling direction may be used. These techniques can be used in both planar and 3D (e.g., FinFET) semiconductor processes.

REFERENCE TO PRIORITY APPLICATIONS

This application is a continuation-in-part of U.S. application Ser. No. 16/524,259, filed Jul. 29, 2019, entitled “Topological Programmable Scalable Quantum Computing Machine Utilizing Chord Line Quasi Unidimensional Aperture Tunneling Semiconductor Structures,” which claims the benefit of U.S. Provisional Application No. 62/687,800, filed Jun. 20, 2018, entitled “Electric Signal Pulse-Width And Amplitude Controlled And Re-Programmable Semiconductor Quantum Rotation Gates,” U.S. Provisional Application No. 62/687,803, filed Jun. 21, 2018, entitled “Semiconductor Quantum Structures and Computing Circuits Using Local Depleted Well Tunneling,” U.S. Provisional Application No. 62/689,100, filed Jun. 23, 2018, entitled “Semiconductor Controlled Entangled-Aperture-Logic Quantum Shift Register,” U.S. Provisional Application No. 62/694,022, filed Jul. 5, 2018, entitled “Double-V Semiconductor Entangled-Aperture-Logic Parallel Quantum Interaction Path,” U.S. Provisional Application No. 62/687,779, filed Jun. 20, 2018, entitled “Semiconductor Quantum Structures And Gates Using Through-Thin-Oxide Well-To-Gate Aperture Tunneling,” U.S. Provisional Application No. 62/687,793, filed Jun. 20, 2018, entitled “Controlled Semiconductor Quantum Structures And Computing Circuits Using Aperture Well-To-Gate Tunneling,” U.S. Provisional Application No. 62/688,341, filed Jun. 21, 2018, entitled “3D Semiconductor Quantum Structures And Computing Circuits Using Fin-To-Gate Tunneling,” U.S. Provisional Application No. 62/689,035, filed Jun. 22, 2018, entitled “3D Semiconductor Quantum Structures And Computing Circuits Using Controlled Tunneling Through Local Fin Depletion Regions,” U.S. Provisional Application No. 62/689,291, filed Jun. 25, 2018, entitled “Semiconductor Quantum Dot And Qubit Structures Using Aperture-Tunneling Through Oxide Layer,” U.S. Provisional Application No. 62/689,166, filed Jun. 24, 2018, entitled “Semiconductor Entangled-Aperture-Logic Quantum Ancillary Gates,” U.S. Provisional Application No. 62/692,745, filed Jun. 20, 2018, entitled “Re-Programmable And Re-Configurable Quantum Processor Using Pulse-Width Based Rotation Selection And Path Access Or Bifurcation Control,” U.S. Provisional Application No. 62/692,804, filed Jul. 1, 2018, entitled “Quantum Processor With Dual-Path Quantum Error Correction,” U.S. Provisional Application No. 62/692,844, filed Jul. 1, 2018, entitled “Quantum Computing Machine With Partial Data Readout And Re-Injection Into The Quantum State,” U.S. Provisional Application No. 62/726,290, filed Jun. 20, 2018, entitled “Controlled-NOT and Tofolli Semiconductor Entangled-Aperture-Logic Quantum Gates,” U.S. Provisional Application No. 62/695,842, filed Jul. 10, 2018, entitled “Entangled Aperture-Logic Semiconductor Quantum Computing Structure with Intermediary Interactor Path,” U.S. Provisional Application No. 62/698,278, filed Jul. 15, 2018, entitled “Entangled Aperture-Logic Semiconductor Quantum Bifurcation and Merging Gate,” U.S. Provisional Application No. 62/726,397, filed Sep. 3, 2018, entitled “Semiconductor Quantum Structure With Simultaneous Shift Into Entangled State,” U.S. Provisional Application No. 62/791,818, filed Jan. 13, 2019, entitled “Semiconductor Process for Quantum Structures with Staircase Active Well,” U.S. Provisional Application No. 62/788,865, filed Jan. 6, 2018, entitled “Semiconductor Process For Quantum Structures Without Inner Contacts And Doping Layers,” U.S. Provisional Application No. 62/794,591, filed Jan. 19, 2019, entitled “Semiconductor Quantum Structures Using Localized Aperture Channel Tunneling Through Controlled Depletion Region,” U.S. Provisional Application No. 62/703,888, filed Jul. 27, 2018, entitled “Aperture Tunneling Semiconductor Quantum Dots and Chord-Line Quantum Computing Structures,” U.S. Provisional Application No. 62/726,271, filed Sep. 2, 2018, entitled “Controlled Local Thermal Activation Of Freeze-Out Semiconductor Circuits For Cryogenic Operation,” U.S. Provisional Application No. 62/731,810, filed Sep. 14, 2018, entitled “Multi-Stage Semiconductor Quantum Detector with Anti-Correlation Merged With Quantum Core,” and U.S. Provisional Application No. 62/794,655, filed Jan. 20, 2019, entitled “Semiconductor Quantum Structures Using Preferential Tunneling Direction Through Thin Insulator Layers.” All of which are incorporated herein by reference in their entirety.

FIELD OF THE DISCLOSURE

The subject matter disclosed herein relates to the field of quantum computing and more particularly relates to semiconductor structures using preferential tunneling through thin insulator layers.

BACKGROUND OF THE INVENTION

Quantum computers are machines that perform computations using the quantum effects between elementary particles, e.g., electrons, holes, ions, photons, atoms, molecules, etc. Quantum computing utilizes quantum-mechanical phenomena such as superposition and entanglement to perform computation. Quantum computing is fundamentally linked to the superposition and entanglement effects and the processing of the resulting entanglement states. A quantum computer is used to perform such computations which can be implemented theoretically or physically.

Currently, analog and digital are the two main approaches to physically implementing a quantum computer. Analog approaches are further divided into quantum simulation, quantum annealing, and adiabatic quantum computation. Digital quantum computers use quantum logic gates to do computation. Both approaches use quantum bits referred to as qubits.

Qubits are fundamental to quantum computing and are somewhat analogous to bits in a classical computer. Qubits can be in a |0> or |1> quantum state but they can also be in a superposition of the |0> and |1> states. When qubits are measured, however, they always yield a |0> or a |1> based on the quantum state they were in.

The key challenge of quantum computing is isolating such microscopic particles, loading them with the desired information, letting them interact and then preserving the result of their quantum interaction. This requires relatively good isolation from the outside world and a large suppression of the noise generated by the particle itself. Therefore, quantum structures and computers operate at very low temperatures (e.g., cryogenic), close to the absolute zero kelvin (K), in order to reduce the thermal energy/movement of the particles to well below the energy/movement coming from their desired interaction. Current physical quantum computers, however, are very noisy and quantum error correction is commonly applied to compensate for the noise.

Most existing quantum computers use superconducting structures to realize quantum interactions. Their main drawbacks, however, are the fact that superconducting structures are very large and costly and have difficulty in scaling to quantum processor sizes of thousands or millions of quantum-bits (qubits). Furthermore, they need to operate at few tens of milli-kelvin (mK) temperatures, that are difficult to achieve and where it is difficult to dissipate significant power to operate the quantum machine.

SUMMARY OF THE INVENTION

The present invention describes a topological, scalable, and reprogrammable quantum computing machine having one or more quasi-unidimensional chord lines along which the movement of a particle is constrained. The unidimensional passage has localized energy levels that can be controlled with classic electronics. The chord line has two or more quantum dots between which a quasi-unidimensional channel is formed for the particle to travel from one qdot to the other. The tunneling path may be polysilicon, metal, thin oxide, or induced depletion region. The chord line can be in a two-dimensional space for a planar process or in a three-dimensional space with multiple layers of signal processing for a three dimensional process. A quantum structure has semiconductor dots with a layer that provides the chord line for the quantum particle evolution to occur from one dot to the other. The various layers may include polysilicon, metal, thin oxide, or induced depletion region either fully overlapped or partially overlapped.

In addition, several quantum structures provide various control functions whereby particles are brought into close proximity so they can interact with one another. Particles relatively far away one from the other have small or negligible interaction. Two or more quantum particles or states brought in close proximity will interact and exchange information. Such particles are “entangled” as each particle carries information from all particles that interacted. After entanglement, the particles are moved away from each other but they still carry the information contained initially. Measurement and detection is performed on the particles from the entangled ensemble to determine whether the particle is present or not in a given qdot.

A quantum interaction gate is a circuit or structure operating on a relatively small number of qubits. The type of quantum interaction gate is given both by the physical/geometrical structure of the gate and by the corresponding control signal. A given geometrical structure may perform different quantum interaction gate functions depending on the control signals applied, including their shape, amplitude, pulse width, duration, position, etc.

Quantum interaction gates implement several quantum functions including a controlled NOT gate, quantum annealing gate, controlled SWAP gate, a controlled rotation (i.e. controlled Pauli) gate, and ancillary gate. These quantum interaction gates can have numerous shapes including double V shape, H shape, X shape, L shape, I shape, etc.

Quantum annealing is the operation of finding the minima of a given function over a given set of candidate solutions using the quantum fluctuation method. The SWAP quantum, interaction gate functions to permute the incoming quantum states. The Pauli quantum interaction gate is a single qubit quantum interaction gate that performs rotation about the z, y, and x axis. Ancillary or ancilla qubits have an unknown value a priori. The Hadamard equal distribution quantum state is an example of an ancilla qubit.

In one embodiment, semiconductor quantum structures are implemented using tunneling through a thin oxide layer. The quantum dots are fabricated with semiconductor wells, 3D fins or combinations thereof, while the tunneling path and any optional quantum transport path is implemented with gate layers. The oxide layer between the gate and the well is thin enough in the nanometer semiconductor processes that they permit significant tunneling. Having a thin oxide layer on only one side of the well, while having thick oxide layers on all other sides, results in a preferential tunneling direction. In alternative embodiments, more than one preferential tunneling direction may be used (e.g., two or even three). These techniques can be used in both planar and 3D (e.g., FinFET) semiconductor processes.

This, additional, and/or other aspects and/or advantages of the embodiments of the present invention are set forth in the detailed description which follows; possibly inferable from the detailed description; and/or learnable by practice of the embodiments of the present invention.

There is thus provided in accordance with the invention, a quantum structure, comprising a substrate, isolation material fabricated on said substrate, a first quantum well and a second quantum well surrounded partially or completely at least on two sides by said isolation material, a quantum transport path fabricated on said isolation layer overlaying said first quantum well and said second quantum well, and operative to provide conduction transport of a quantum particle therebetween, a first preferential tunneling path between said first quantum well and said quantum transport path, and a second preferential tunneling path between said second quantum well and said quantum transport path.

There is also provided in accordance with the invention, a quantum structure, comprising a substrate, isolation material fabricated on said substrate, a semiconductor well surrounded partially or completely at least on two sides by said isolation material, a back gate layer fabricated below said semiconductor well, a front gate layer fabricated above said semiconductor well, a first preferential tunneling path between said semiconductor well and said back gate, and a second preferential tunneling path between said semiconductor well and said front gate.

There is further provided in accordance with the invention, a method of fabricating a quantum structure, comprising providing a substrate material, fabricating isolation material on said substrate, fabricating a first quantum well and a second quantum well surrounded partially or completely on at least two sides by said isolation material, fabricating a quantum transport path on said isolation material overlaying said first quantum well and said second quantum well, and operative to provide conduction transport of a quantum particle between said first quantum well to said second quantum well, forming a first preferential tunneling path between said first quantum well and said quantum transport path, and forming a second preferential tunneling path between said second quantum well and said quantum transport path.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is explained in further detail in the following exemplary embodiments and with reference to the figures, where identical or similar elements may be partly indicated by the same or similar reference numerals, and the features of various exemplary embodiments being combinable. The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:

FIG. 1 is a high level block diagram illustrating an example quantum computer system constructed in accordance with the present invention;

FIG. 2 is a high level block diagram illustrating a quantum structure and its interface using integrated electronic control circuitry;

FIG. 3A is a diagram illustrating a quantum structure before initialization;

FIG. 3B is a diagram illustrating an example ideal and decoherence Rabi oscillation waveform;

FIG. 3C is a diagram illustrating a quantum structure initialized to a first base state;

FIG. 3D is a diagram illustrating an example Rabi oscillation waveform at initialization;

FIG. 3E is a diagram illustrating a quantum structure initialized to a second base state;

FIG. 3F is a diagram illustrating an example waveform having half the Rabi oscillation period;

FIG. 3G is a diagram illustrating a quantum structure with a particle in two qdots at the same time;

FIG. 3H is a diagram illustrating an example waveform having one quarter the Rabi oscillation period;

FIG. 3I is a diagram illustrating a first quantum structure with a particle split between two qdots at the same time;

FIG. 3J is a diagram illustrating an example waveform having a period less than one quarter the Rabi oscillation period;

FIG. 3K is a diagram illustrating a second quantum structure with a particle split between two qdots at the same time;

FIG. 3L is a diagram illustrating an example waveform having a period more than one quarter the Rabi oscillation period;

FIG. 4A is a diagram illustrating a circular shaped quantum structure incorporating local depleted well tunneling;

FIG. 4B is a diagram illustrating the change in the aperture tunnel barrier from a wide depletion region to a narrow depletion region;

FIG. 4C is a diagram illustrating a first rectangular shaped quantum structure incorporating local depleted well tunneling;

FIG. 4D is a diagram illustrating the change in the aperture tunnel barrier from a wide depletion region to a narrow depletion region;

FIG. 5 is a diagram illustrating a second rectangular shaped quantum structure incorporating local depleted well tunneling;

FIG. 6 is a diagram illustrating a cross section of an example quantum structure;

FIG. 7A is a diagram illustrating an example circular shape for the quantum structure of the present invention;

FIG. 7B is a diagram illustrating an example square shape for the quantum structure of the present invention;

FIG. 7C is a diagram illustrating an example square shape with rounded corners for the quantum structure of the present invention;

FIG. 7D is a diagram illustrating an example hexagonal shape for the quantum structure of the present invention;

FIG. 7E is a diagram illustrating an example rectangular shape for the quantum structure of the present invention;

FIG. 7F is a diagram illustrating an example trapezoidal shape for the quantum structure of the present invention;

FIG. 7G is a diagram illustrating a first example overlapping square shape for the quantum structure of the present invention;

FIG. 7H is a diagram illustrating a first example ‘L’ shape for the quantum structure of the present invention;

FIG. 7I is a diagram illustrating an example ‘Z’ shape for the quantum structure of the present invention;

FIG. 7J is a diagram illustrating a second example ‘L’ shape for the quantum structure of the present invention;

FIG. 7K is a diagram illustrating an example barely touching square shape for the quantum structure of the present invention;

FIG. 7L is a diagram illustrating an example barely touching square shape with optical proximity control for the quantum structure of the present invention;

FIG. 7M is a diagram illustrating an example double square with narrow neck shape for the quantum structure of the present invention;

FIG. 7N is a diagram illustrating a second example overlapping square shape for the quantum structure of the present invention;

FIG. 7O is a diagram illustrating a third example overlapping square shape for the quantum structure of the present invention;

FIG. 7P is a diagram illustrating an example barely touching rectangular shape for the quantum structure of the present invention;

FIG. 7Q is a diagram illustrating an example barely touching double overlapping square shape for the quantum structure of the present invention;

FIG. 7R is a diagram illustrating an example double square connected via single smaller square shape for the quantum structure of the present invention;

FIG. 7S is a diagram illustrating an example double square connected via double smaller square shape for the quantum structure of the present invention;

FIG. 8A is a diagram illustrating a first example control gate for the quantum structure of the present invention;

FIG. 8B is a diagram illustrating a second example control gate for the quantum structure of the present invention;

FIG. 8C is a diagram illustrating a third example control gate for the quantum structure of the present invention;

FIG. 9A is a diagram illustrating an example quantum structure with double square shape;

FIG. 9B is a diagram illustrating an example quantum structure with double square shape and optical proximity control;

FIG. 9C is a diagram illustrating an example quantum structure with double square and narrow neck shape;

FIG. 9D is a diagram illustrating a first example quantum structure with double overlapping square shape;

FIG. 9E is a diagram illustrating a second example quantum structure with double overlapping square shape;

FIG. 9F is a diagram illustrating an example quantum structure with ‘L’ shape;

FIG. 9G is a diagram illustrating an example quantum structure with double rounded barely touching square shape;

FIG. 9H is a diagram illustrating an example quantum structure with double rectangular shape;

FIG. 9I is a diagram illustrating an example quantum structure with double square connected via double smaller square shape;

FIG. 9J is a diagram illustrating an example quantum structure with double rounded square with narrow neck shape;

FIG. 9K is a diagram illustrating an example quantum structure with an overlapping pair of double rounded squares with narrow neck shape;

FIG. 9L is a diagram illustrating a first example quantum structure with a pair of barely touching double overlapping square shape;

FIG. 9M is a diagram illustrating a second example quantum structure with a pair of barely touching double overlapping square shape;

FIG. 9N is a diagram illustrating a first example quantum structure with a double square shape with narrow neck and butterfly shaped control gate;

FIG. 9O is a diagram illustrating a second example quantum structure with a double square shape with narrow neck and butterfly shaped control gate;

FIG. 9P is a diagram illustrating an example quantum structure with a pair of overlapping double square shapes with narrow neck and butterfly shaped control gates;

FIG. 9Q is a diagram illustrating an example conventional FET with drain and source doped diffusion and contacts;

FIG. 9R is a diagram illustrating an example half conventional FET and half quantum structure;

FIG. 9S is a diagram illustrating an example quantum structure with rectangular shaped wells;

FIG. 9T is a diagram illustrating an example quantum structure with dissimilar rectangular shaped wells;

FIG. 9U is a diagram illustrating an example quantum structure with offset rectangular shaped wells;

FIG. 9V is a diagram illustrating a first example quantum structure with spaced apart rectangular shaped wells;

FIG. 9W is a diagram illustrating a first example quantum structure with spaced apart rectangular shaped wells offset from each other;

FIG. 9X is a diagram illustrating a second example quantum structure with spaced apart rectangular shaped wells;

FIG. 9Y is a diagram illustrating a second example quantum structure with spaced apart rectangular shaped wells offset from each other;

FIG. 9Z is a diagram illustrating a third example quantum structure with spaced apart rectangular shaped wells offset from each other;

FIG. 9AA is a diagram illustrating a fourth example quantum structure with spaced apart rectangular shaped wells offset from each other;

FIG. 9AB is a diagram illustrating a first example quantum structure with corner abutting rectangular shaped wells;

FIG. 9AC is a diagram illustrating a second example quantum structure with corner abutting rectangular shaped wells;

FIG. 9AD is a diagram illustrating a third example quantum structure with corner abutting rectangular shaped wells;

FIG. 9AE is a diagram illustrating a fourth example quantum structure with corner abutting rectangular shaped wells;

FIG. 9AF is a diagram illustrating a fifth example quantum structure with corner abutting rectangular shaped wells;

FIG. 9AG is a diagram illustrating a sixth example quantum structure with corner abutting rectangular shaped wells;

FIG. 10A is a diagram illustrating a first example interface device of the present invention in more detail;

FIG. 10B is a diagram illustrating a second example interface device of the present invention;

FIG. 10C is a diagram illustrating a third example interface device of the present invention;

FIG. 11 is a diagram illustrating a cross section of a first example quantum structure and conventional FET;

FIG. 12 is a diagram illustrating a cross section of a second example quantum structure and conventional FET;

FIG. 13 is a diagram illustrating a cross section of a third example quantum structure and conventional FET;

FIG. 14 is a diagram illustrating an example quantum structure with interface devices;

FIG. 15A is a diagram illustrating a first example multiple qdot quantum structure with interface devices on either end thereof;

FIG. 15B is a diagram illustrating an example layout of an example quantum structure;

FIG. 16 is a diagram illustrating a cross section of the quantum structure of FIG. 15A;

FIG. 17A is a diagram illustrating the aperture tunnel barrier for a two quantum dot structure;

FIG. 17B is a diagram illustrating a first example change in the aperture tunnel barrier for the two quantum dot structure;

FIG. 17C is a diagram illustrating a second example change in the aperture tunnel barrier for the two quantum dot structure;

FIG. 18 is a diagram illustrating an example quantum structure surrounded by a spin control magnetic coil;

FIG. 19 is a diagram illustrating a second example multiple qdot quantum structure;

FIG. 20 is a diagram illustrating a third example multiple qdot quantum structure;

FIG. 21 is a diagram illustrating a fourth example multiple qdot quantum structure;

FIG. 22A is a diagram illustrating an example floating well detection circuit;

FIG. 22B is a diagram illustrating the layout for the example floating well detection circuit;

FIG. 22C is a diagram illustrating the cross section for the floating well detection circuit;

FIG. 23A is a diagram illustrating an example floating gate detection circuit;

FIG. 23B is a diagram illustrating the layout for the example floating gate detection circuit;

FIG. 23C is a diagram illustrating the cross section for the floating gate detection circuit;

FIG. 24 is an example potential diagram for the floating gate detection circuit;

FIG. 25 is a diagram illustrating an example 3D semiconductor quantum structure using fin to fin tunneling through local depletion region;

FIG. 26 is a diagram illustrating a three dimensional view of an example 3D semiconductor quantum structure with fin to fin tunneling under control of a control gate;

FIG. 27A is a diagram illustrating a cross section, side view, and top view of an example 3D two qdot quantum structure using local fin depletion tunneling;

FIG. 27B is a diagram illustrating a cross section, side views, and top view of an example 3D multiple qdot quantum structure using local fin depletion tunneling;

FIG. 28A is a diagram illustrating two example double V fin-gate-fin structures having two wells placed in close proximity allowing quantum particles to interact;

FIG. 28B is a diagram illustrating an example 3D semiconductor quantum structure using fin-to-fin tunneling through a local depleted region with a shared well between two fin paths providing bifurcation;

FIG. 28C is a diagram illustrating an example quantum structure with dummy gates and gate cuts that separate control and dummy gates;

FIG. 28D is a diagram illustrating an example hybrid planar and 3D semiconductor quantum structure using both fin-to-fin and well-to-well tunneling through local depletion region;

FIG. 29 is a diagram illustrating an example 3D semiconductor quantum structure using fin-to-gate tunneling through oxide;

FIG. 30 is a diagram illustrating a three dimensional view of an example 3D semiconductor quantum structure using fin-to-gate and gate-to-fin tunneling through oxide;

FIG. 31 is a diagram illustrating a cross section, side view, and top view of an example 3D semiconductor quantum structure using fin-to-gate tunneling through oxide;

FIG. 32 is a diagram illustrating a cross section of an example 3D semiconductor quantum structure using fin-to-gate and gate-to-fin tunneling;

FIG. 33 is a diagram illustrating a top view of an example two qdot 3D semiconductor quantum structure using fin-to-gate tunneling through oxide;

FIG. 34A is a diagram illustrating an example double V quantum interaction structure using 3D semiconductor process with fin-to-gate tunneling;

FIG. 34B is a diagram illustrating an example quantum structure with fin-to-gate tunneling with dummy gates and cuts to create dummy fins;

FIG. 34C is a diagram illustrating an example hybrid planar and 3D semiconductor quantum structure using both fin-to-gate and well-to-gate tunneling;

FIG. 35 is a diagram illustrating an example initialization configuration for a quantum interaction structure using tunneling through gate-well oxide layer;

FIG. 36 is a diagram illustrating an example initialization configuration for a quantum interaction structure using tunneling through local depleted region in a continuous well;

FIG. 37A is a diagram illustrating an example planar semiconductor quantum structure using tunneling through oxide layer;

FIG. 37B is a diagram illustrating an example planar semiconductor quantum structure using tunneling through local depleted well;

FIG. 37C is a diagram illustrating an example 3D process semiconductor quantum structure using tunneling through oxide layer;

FIG. 37D is a diagram illustrating an example 3D process semiconductor quantum structure using tunneling through local depleted well;

FIG. 38A is a diagram illustrating an example CNOT quantum interaction gate using tunneling through oxide layer implemented in planar semiconductor processes;

FIG. 38B is a diagram illustrating an example CNOT quantum interaction gate using tunneling through local depleted well implemented in planar semiconductor processes;

FIG. 38C is a diagram illustrating an example CNOT quantum interaction gate using tunneling through oxide layer implemented in 3D semiconductor processes;

FIG. 38D is a diagram illustrating an example CNOT quantum interaction gate using tunneling through local depleted fin implemented in 3D semiconductor processes;

FIG. 39 is a diagram illustrating a first example of semiconductor entanglement quantum interaction gate including initialization, staging, interaction, and output locations;

FIG. 40A is a diagram illustrating an example semiconductor qubit using tunneling through a separate layer planar structure;

FIG. 40B is a diagram illustrating an example semiconductor qubit using tunneling through a local depleted well planar structure;

FIG. 40C is a diagram illustrating an example semiconductor qubit using tunneling through a separate layer 3D FIN-FET structure;

FIG. 40D is a diagram illustrating an example semiconductor qubit using tunneling through a local depleted well 3D FIN-FET structure;

FIG. 40E is a diagram illustrating a semiconductor CNOT quantum interaction gate using two qubit double qdot structures with tunneling through a separate structure planar structure;

FIG. 40F is a diagram illustrating a first example quantum interaction gate with interaction between two particles in the same continuous well;

FIG. 40G is a diagram illustrating a second example quantum interaction gate with interaction between two particles in the same continuous well;

FIG. 40H is a diagram illustrating a third example quantum interaction gate with interaction between two particles in the same continuous well;

FIG. 40I is a diagram illustrating a first example quantum interaction gate with interaction between two particles in different continuous wells;

FIG. 40J is a diagram illustrating a second example quantum interaction gate with interaction between two particles in different continuous wells;

FIG. 40K is a diagram illustrating a second example quantum interaction gate with interaction between two particles in different continuous wells;

FIG. 40L is a diagram illustrating a second example quantum interaction gate with interaction between two particles in different continuous wells;

FIG. 41 is a diagram illustrating an example quantum interaction gate with continuous well incorporating reset, inject, impose, and detect circuitry;

FIG. 42 is a diagram illustrating an example double V CNOT quantum interaction gate using common control gates for sections in closer proximity to permit smaller spacing and stronger interaction;

FIG. 43A is a diagram illustrating a first example CNOT quantum interaction gate using 3D FIN-FET semiconductor process with tunneling through separate layer and interaction from enlarged well islands allowing smaller spacing and stronger interaction;

FIG. 43B is a diagram illustrating a second example CNOT quantum interaction gate using 3D FIN-FET semiconductor process with tunneling through separate layer and interaction from enlarged well islands allowing smaller spacing and stronger interaction;

FIG. 43C is a diagram illustrating a third example CNOT quantum interaction gate using 3D FIN-FET semiconductor process with interaction from enlarged well islands allowing smaller spacing and stronger interaction;

FIG. 43D is a diagram illustrating a fourth example CNOT quantum interaction gate using 3D FIN-FET semiconductor process with fin to fin interaction mandating larger spacing and weaker interaction;

FIG. 44A is a diagram illustrating an example qdot with multidimensional tunneling and multiple clusters of energy levels;

FIG. 44B is a diagram illustrating an example qdot with unidimensional tunneling and two well separated energy levels;

FIG. 45A is a diagram illustrating an example double qdot structure with full overlap of the control gate over the quantum wells;

FIG. 45B is a diagram illustrating example double qdot structure with controlled tunneling between two quantum wells;

FIG. 45C is a diagram illustrating variation of potential in a double qdot structure with controlled tunneling between the two quantum wells;

FIG. 46A is a diagram illustrating an example quantum structure using tunneling through thin oxide with full overlap of the gate over the quantum wells;

FIG. 46B is a diagram illustrating an example quantum structure using tunneling through thin oxide with partial overlap on the edge of the gate over the quantum wells;

FIG. 46C is a diagram illustrating an example quantum structure using tunneling through thin oxide with partial overlap on the corners of the gate over the quantum wells;

FIG. 47A is a diagram illustrating a general tunneling path implementation between two quantum dots;

FIG. 47B is a diagram illustrating a polysilicon tunneling path implementation between two quantum dots;

FIG. 47C is a diagram illustrating a metal tunneling path implementation between two quantum dots;

FIG. 47D is a diagram illustrating a local depletion tunneling path implementation between two quantum dots;

FIG. 48A is a diagram illustrating a first polysilicon tunneling path implementation between two quantum dots using a 3D process;

FIG. 48B is a diagram illustrating a second polysilicon tunneling path implementation between two quantum dots using a 3D process;

FIG. 48C is a diagram illustrating a metal tunneling path implementation between two quantum dots using a 3D process;

FIG. 48D is a diagram illustrating a local depletion tunneling path implementation between two quantum dots using a 3D process;

FIG. 49A is a diagram illustrating a cross section of a planar semiconductor process of a quantum structure with tunneling through depletion region and metal tunneling control;

FIG. 49B is a diagram illustrating a cross section of a planar semiconductor process of a quantum structure with tunneling through thin oxide layer and metal tunneling control;

FIG. 50A is a diagram illustrating quasi-unidimensional vertical tunneling;

FIG. 50B is a diagram illustrating quasi-unidimensional horizontal tunneling;

FIG. 51A is a diagram illustrating a planar semiconductor process cross section with polysilicon tunneling path and several control options;

FIG. 51B is a diagram illustrating a planar semiconductor process cross section with metal tunneling path and control;

FIG. 51C is a diagram illustrating a 3D semiconductor process cross section with different control options;

FIG. 52 is a diagram illustrating carrier energy level distribution at room temperature and cryogenic temperatures;

FIG. 53 is a diagram illustrating an example semiconductor structure using two preferential direction tunneling and a supplementary transport path;

FIG. 54A is a diagram illustrating a first example semiconductor structure using preferential tunneling;

FIG. 54B is a diagram illustrating a second example semiconductor structure using preferential tunneling;

FIG. 54C is a diagram illustrating a third example semiconductor structure using preferential tunneling;

FIG. 54D is a diagram illustrating a fourth example semiconductor structure using preferential tunneling;

FIG. 54E is a diagram illustrating a fifth example semiconductor structure using preferential tunneling;

FIG. 54F is a diagram illustrating a sixth example semiconductor structure using preferential tunneling;

FIG. 54G is a diagram illustrating a seventh example semiconductor structure using preferential tunneling;

FIG. 55 is a diagram illustrating an example semiconductor well with thin insulation layer on one side;

FIG. 56 is a diagram illustrating an example of two semiconductor wells with thin insulation layer on one side and a quantum transport path;

FIG. 57A is a diagram illustrating an example planar semiconductor structure with a quantum transport path through full overlapping polysilicon gate;

FIG. 57B is a diagram illustrating an example planar semiconductor structure with a quantum transport path through full overlapping metal gate;

FIG. 58A is a diagram illustrating a first example 3D semiconductor structure with a quantum transport path through full overlapping polysilicon gate;

FIG. 58B is a diagram illustrating an example 3D semiconductor structure with a quantum transport path through full overlapping metal gate;

FIG. 59A is a diagram illustrating an example semiconductor structure with full overlap gate layer over the well;

FIG. 59B is a diagram illustrating an example semiconductor structure with partial overlap gate layer over the well;

FIG. 60A is a diagram illustrating an example quantum structure with full center well to gate overlap;

FIG. 60B is a diagram illustrating an example quantum structure with full side well to gate overlap;

FIG. 60C is a diagram illustrating an example quantum structure with partial center well to gate overlap;

FIG. 60D is a diagram illustrating an example quantum structure with partial side well to gate overlap;

FIG. 61 is a diagram illustrating an example double qdot quantum structure using preferential tunneling on one side through thin oxide;

FIG. 62A is a diagram illustrating a first example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer;

FIG. 62B is a diagram illustrating a second example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer;

FIG. 62C is a diagram illustrating a third example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer;

FIG. 62D is a diagram illustrating a fourth example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer;

FIG. 62E is a diagram illustrating a fifth example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer;

FIG. 62F is a diagram illustrating a sixth example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer;

FIG. 62G is a diagram illustrating a seventh example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer;

FIG. 63 is a diagram illustrating example preferential tunneling through thin oxide in a planar bulk semiconductor process with reverse biased junction isolation;

FIG. 64 is a diagram illustrating example preferential tunneling through thin oxide in a planar SOI semiconductor process with buried thick oxide and thick side trench oxide layers;

FIG. 65 is a diagram illustrating an example double quantum dot semiconductor quantum structure using planar SOI process with preferential tunneling between the well and gate;

FIG. 66 is a diagram illustrating example pair of double quantum dot semiconductor quantum structures using preferential tunneling and placed in close proximity to enable interaction between them;

FIG. 67A is a diagram illustrating an example semiconductor quantum structure using preferential tunneling on two sides with front and back gates and full gate to well overlap;

FIG. 67B is a diagram illustrating an example semiconductor quantum structure using preferential tunneling on two sides with front and back gates and partial gate to well overlap;

FIG. 67C is a diagram illustrating an example 3D semiconductor quantum structure with three preferential tunneling directions around a fin based quantum well;

FIG. 67D is a diagram illustrating an example double quantum dot 3D semiconductor quantum structure with three preferential tunneling directions around a fin based quantum well;

FIG. 67E is a diagram illustrating an example 3D semiconductor quantum structure with preferential tunneling on one side only through this oxide;

FIG. 68A is a diagram illustrating a first example semiconductor quantum structure using a composed shape to realize a double quantum dot with preferential tunneling;

FIG. 68B is a diagram illustrating a second example semiconductor quantum structure using a composed shape to realize a double quantum dot with preferential tunneling;

FIG. 69A is a diagram illustrating an example potential distribution in a three quantum dot semiconductor quantum structure with large tunneling barrier and tunneling time;

FIG. 69B is a diagram illustrating an example potential distribution in a three quantum dot semiconductor quantum structure with lower tunneling barrier;

FIG. 69C is a diagram illustrating an example potential distribution in a three quantum dot semiconductor quantum structure with the barrier raised after the particle has tunneled;

FIG. 69D is a diagram illustrating an example potential distribution in a three quantum dot semiconductor quantum structure where the particles are allowed to interact and tunnel;

FIG. 70 is a diagram illustrating a cross section of an example semiconductor quantum structure using preferential tunneling with a metal control terminal layer in proximity of the gate;

FIG. 71A is a diagram illustrating the use of a buried oxide layer to isolate quantum wells from the substrate in an SOI process based quantum structure with preferential tunneling to minimize parasitic interaction;

FIG. 71B is a diagram illustrating substrate elimination in an SOI process based quantum structure with preferential tunneling to minimize parasitic interaction;

FIG. 71C is a diagram illustrating substrate thinning in an SOI process based quantum structure with preferential tunneling to minimize parasitic interaction;

FIG. 71D is a diagram illustrating substrate replacement with inert material in an SOI process based quantum structure with preferential tunneling to minimize parasitic interaction;

FIG. 72 is a diagram illustrating an example 3D semiconductor quantum structure using preferential tunneling direction and impower metal to set the potential on the floating gate;

FIG. 73A is a diagram illustrating an example semiconductor quantum structure using preferential tunneling direction implemented in a planar semiconductor process using rectangular well and gate shapes and full gate-to-well overlap; and

FIG. 73B is a diagram illustrating an example semiconductor quantum structure using preferential tunneling direction implemented in a planar semiconductor process using rectangular well and gate shapes and partial gate-to-well overlap.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be understood by those skilled in the art, however, that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

Among those benefits and improvements that have been disclosed, other objects and advantages of this invention will become apparent from the following description taken in conjunction with the accompanying figures. Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the invention that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the invention which are intended to be illustrative, and not restrictive.

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.

The figures constitute a part of this specification and include illustrative embodiments of the present invention and illustrate various objects and features thereof. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. In addition, any measurements, specifications and the like shown in the figures are intended to be illustrative, and not restrictive. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

Any reference in the specification to a method should be applied mutatis mutandis to a system capable of executing the method. Any reference in the specification to a system should be applied mutatis mutandis to a method that may be executed by the system.

Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The phrases “in one embodiment,” “in an example embodiment,” and “in some embodiments” as used herein do not necessarily refer to the same embodiment(s), though it may. Furthermore, the phrases “in another embodiment,” “in an alternative embodiment,” and “in some other embodiments” as used herein do not necessarily refer to a different embodiment, although it may. Thus, as described below, various embodiments of the invention may be readily combined, without departing from the scope or spirit of the invention.

In addition, as used herein, the term “or” is an inclusive “or” operator, and is equivalent to the term “and/or,” unless the context clearly dictates otherwise. The term “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise. In addition, throughout the specification, the meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

The following definitions apply throughout this document.

A quantum particle is defined as any atomic or subatomic particle suitable for use in achieving the controllable quantum effect. Examples include electrons, holes, ions, photons, atoms, molecules, artificial atoms. A carrier is defined as an electron or a hole in the case of semiconductor electrostatic qubit. Note that a particle (actually its wavefunction) may be split and present in multiple quantum dots. Thus, a reference to a particle also includes split particles.

In quantum computing, the qubit is the basic unit of quantum information, i.e. the quantum version of the classical binary bit physically realized with a two-state device. A qubit is a two base state quantum mechanical system in which the states can be in a superposition. Examples include (1) the spin of the particle (e.g., electron, hole) in which the two levels can be taken as spin up and spin down; (2) the polarization of a single photon in which the two states can be taken to be the vertical polarization and the horizontal polarization; and (3) the position of the particle (e.g., electron) in a structure of two qdots, in which the two states correspond to the particle being in one qdot or the other. In a classical system, a bit is in either one state or the other. Quantum mechanics, however, allows the qubit to be in a coherent superposition of both states simultaneously, a property fundamental to quantum mechanics and quantum computing. Multiple qubits can be further entangled with each other.

A quantum dot or qdot (also referred to in literature as QD) is a nanometer-scale structure where the addition or removal of a particle changes its properties is some ways. In one embodiment, quantum dots are constructed in silicon semiconductor material having typical dimension in nanometers. The position of a particle in a qdot can attain several states. Qdots are used to form qubits and qudits where multiple qubits or qudits are used as a basis to implement quantum processors and computers.

A quantum interaction gate is defined as a basic quantum logic circuit operating on a small number of qubits or qudits. They are the building blocks of quantum circuits, just like the classical logic gates are for conventional digital circuits.

A qubit or quantum bit is defined as a two state (two level) quantum structure and is the basic unit of quantum information. A qudit is defined as a d-state (d-level) quantum structure. A qubyte is a collection of eight qubits.

The terms control gate and control terminal are intended to refer to the semiconductor structure fabricated over a continuous well with a local depleted region and which divides the well into two or more qdots. These terms are not to be confused with quantum gates or classical field effect transistor (FET) gates.

Unlike most classical logic gates, quantum logic gates are reversible. It is possible, however, although cumbersome in practice, to perform classical computing using only reversible gates. For example, the reversible Toffoli gate can implement all Boolean functions, often at the cost of having to use ancillary bits. The Toffoli gate has a direct quantum equivalent, demonstrating that quantum circuits can perform all operations performed by classical circuits.

A quantum well is defined as a very small (e.g., typically nanometer scale) two dimensional area of metal or semiconductor that functions to contain a single or a small number of quantum particles. It differs from a classic semiconductor well which might not attempt to contain a small number of particles or/and preserve their quantum properties. One purpose of the quantum well is to realize a function of a qubit or qudit. It attempts to approximate a quantum dot, which is a mathematical zero-dimensional construct. The quantum well can be realized as a low doped or undoped continuous depleted semiconductor well partitioned into smaller quantum wells by means of control gates. The quantum well may or may not have contacts and metal on top. A quantum well holds one free carrier

A classic well is a medium or high doped semiconductor well contacted with metal layers to other devices and usually has a large number of free carriers that behave in a collective way, sometimes denoted as a “sea of electrons.”

A quantum structure or circuit is a plurality of quantum interaction gates. A quantum computing core is a plurality of quantum structures. A quantum computer is a circuit having one or more computing cores. A quantum fabric is a collection of quantum structures, circuits, or interaction gates arranged in a grid like matrix where any desired signal path can be configured by appropriate configuration of access control gates placed in access paths between qdots and structures that make up the fabric.

In one embodiment, qdots are fabricated in low doped or undoped continuous depleted semiconductor wells. Note that the term ‘continuous’ as used herein is intended to mean a single fabricated well (even though there could be structures on top of them, such as gates, that modulate the local well's behavior) as well as a plurality of abutting contiguous wells fabricated separately or together, and in some cases might apparently look as somewhat discontinuous when ‘drawn’ using a computer aided design (CAD) layout tool.

The term classic or conventional circuitry (as opposed to quantum structures or circuits) is intended to denote conventional semiconductor circuitry used to fabricate transistors (e.g., FET, CMOS, BJT, FinFET, etc.) and integrated circuits using processes well-known in the art.

The term Rabi oscillation is intended to denote the cyclic behavior of a quantum system either with or without the presence of an oscillatory driving field. The cyclic behavior of a quantum system without the presence of an oscillatory driving field is also referred to as occupancy oscillation.

Throughout this document, a representation of the state of the quantum system in spherical coordinates includes two angles θ and φ. Considering a unitary sphere, as the Hilbert space is a unitary state, the state of the system is completely described by the vector W. The vector W in spherical coordinates can be described in two angles θ and φ. The angle θ is between the vector W and the z-axis and the angle φ is the angle between the projection of the vector on the XY plane and the x-axis. Thus, any position on the sphere is described by these two angles θ and φ. Note that for one qubit angle θ representation is in three dimensions. For multiple qubits θ representation is in higher order dimensions.

Semiconductor Processing

Regarding semiconductor processing, numerous types of semiconductor material exist such as (1) single main atom types, e.g., Silicon (Si), Germanium (Ge), etc., and (2) compound material types, e.g., Silicon-Germanium (SiGe), Indium-Phosphide (InP), Gallium-Arsenide (GaAs), etc.

A semiconductor layer is called intrinsic or undoped if no additional dopant atoms are added to the base semiconductor crystal network. A doped semiconductor layer is doped if other atoms (i.e. dopants) are added to the base semiconductor crystal. The type of layer depends on the concentration of dopant atoms that are added: (1) very low doped semiconductor layers having high resistivity, i.e. n-type denoted by n−− and p-type denoted by p−−, having resistivities above 100 Ohm·cm; (2) low doped semiconductor layers, i.e. p-type denoted with p- and n-type denoted with n−, having resistivities around 10 Ohm·cm; (3) medium doped layers, i.e. p for p-type and n for n-type; (4) high doped layers, i.e. p+ and n+; and (5) very highly doped layers, i.e. p++ and n++.

Note that introducing dopants in a semiconductor crystal likely results in defects that introduce energy traps that capture mobile carriers. Traps are detrimental for semiconductor quantum structures because they capture and interact with the quantum particles resulting in decoherence of the quantum information. For realizing semiconductor quantum structures undoped semiconductor layers are preferred.

Classic electronic devices use mostly low, medium, high and very highly doped semiconductor layers. Some layers are ultra-highly doped to behave as metals, such as the gate layer.

Semiconductor processing is typically performed on large semiconductor wafers which have a given thickness for mechanical stability. Circuitry is fabricated on a very thin layer on the top of the wafer where the unused thick portion of the wafer is termed the substrate. In a bulk process, devices are fabricated directly in the semiconductor body of the wafer.

An insulating layer (e.g., oxide) isolates from the substrate the devices used to create circuitry. Semiconductor on insulator process, e.g., silicon on insulator (SOI), uses a layer of insulator (e.g., oxide) between the thin top semiconductor layer where devices are realized and the substrate.

To improve circuit performance, the wafer is processed such that the devices are realized on top of an insulator substrate, e.g., semiconductor-on-glass, semiconductor-on-organic material, semiconductor-on-sapphire, etc.

Alternatively, the semiconductor substrate is eliminated and replaced with a nonelectrical conducting material such as a polymer or other material compatible with a semiconductor process (e.g., substrate-replacement processes). Substrate replacement in realizing semiconductor quantum structures significantly reduces or eliminates substrate decoherence.

High resistivity (i.e. very low doped) substrates are the next best substrate choice for semiconductor quantum structures. Although intrinsic substrates are also suitable for semiconductor quantum structures, there are specific limitations that prevent the use of intrinsic substrates.

Thus, in accordance with the invention, semiconductor quantum structures can be realized in (1) bulk processes, (2) SOI processes, (3) substrate replacement processes, or (4) semiconductor on other materials.

Regarding processing, (1) planar processes may be used where layers have predominantly one orientation, i.e. horizontal; and (2) three-dimensional processes (3D) allow layers with both horizontal and vertical orientation, realizing more complex 3D structures. It is appreciated that although layers are shown in the figures as rectangular prisms for simplicity, physically the layers have more complicated structures. For example, corners are often rounded and distortions are present due to the masking process. In depth dimension, layers tend to have a trapezoidal shape instead of the ideal rectangular one. The semiconductor quantum structures of the present invention can be realized in either planar or 3D processes.

Quantum Computing System

A high-level block diagram illustrating a first example quantum computer system constructed in accordance with the present invention is shown in FIG. 1. The quantum computer, generally referenced 10, comprises a conventional (i.e. not a quantum circuit) external support unit 12, software unit 20, cryostat unit 36, quantum processing unit 38, clock generation units 33, 35, and one or more communication busses between the blocks. The external support unit 12 comprises operating system (OS) 18 coupled to communication network 76 such as LAN, WAN, PAN, etc., decision logic 16, and calibration block 14. Software unit 20 comprises control block 22 and digital signal processor (DSP) 24 blocks in communication with the OS 18, calibration engine/data block 26, and application programming interface (API) 28.

Quantum processing unit 38 comprises a plurality of quantum core circuits 60, high speed interface 58, detectors/samplers/output buffers 62, quantum error correction (QEC) 64, digital block 66, analog block 68, correlated data sampler (CDS) 70 coupled to one or more analog to digital converters (ADCs) 74 as well as one or more digital to analog converters (DACs, not shown), clock/divider/pulse generator circuit 42 coupled to the output of clock generator 35 which comprises high frequency (HF) generator 34. The quantum processing unit 38 further comprises serial peripheral interface (SPI) low speed interface 44, cryostat software block 46, microcode 48, command decoder 50, software stack 52, memory 54, and pattern generator 56. The clock generator 33 comprises low frequency (LF) generator 30 and power amplifier (PA) 32, the output of which is input to the quantum processing unit (QPU) 38. Clock generator 33 also functions to aid in controlling the spin of the quantum particles in the quantum cores 60.

The cryostat unit 36 is the mechanical system that cools the QPU down to cryogenic temperatures. Typically, it is made from metal and it can be fashioned to function as a cavity resonator 72. It is controlled by cooling unit control 40 via the external support unit 12. The cooling unit control 40 functions to set and regulate the temperature of the cryostat unit 36. By configuring the metal cavity appropriately, it is made to resonate at a desired frequency. A clock is then driven via a power amplifier which is used to drive the resonator which creates a magnetic field. This magnetic field can function as an auxiliary magnetic field to aid in controlling one or more quantum structures in the quantum core.

The external support unit/software units may comprise any suitable computing device or platform such as an FPGA/SoC board. In one embodiment, it comprises one or more general purpose CPU cores and optionally one or more special purpose cores (e.g., DSP core, floating point, etc.) that that interact with the software stack that drives the hardware, i.e. the QPU. The one or more general purpose cores execute general purpose opcodes while the special purpose cores execute functions specific to their purpose. Main memory comprises dynamic random access memory (DRAM) or extended data out (EDO) memory, or other types of memory such as ROM, static RAM, flash, and non-volatile static random access memory (NVSRAM), bubble memory, etc. The OS may comprise any suitable OS capable of running on the external support unit and software units, e.g., Windows, MacOS, Linux, QNX, NetBSD, etc. The software stack includes the API, the calibration and management of the data, and all the necessary controls to operate the external support unit itself.

The clock generated by the high frequency clock generator 35 is input to the clock divider 42 that functions to generate the signals that drive the QPU. Low frequency clock signals are also input to and used by the QPU. A slow serial/parallel interface (SPI) 44 functions to handle the control signals to configure the quantum operation in the QPU. The high speed interface 58 is used to pump data from the classic computer, i.e. the external support unit, to the QPU. The data that the QPU operates on is provided by the external support unit.

Non-volatile memory may include various removable/non-removable, volatile/nonvolatile computer storage media, such as hard disk drives that reads from or writes to non-removable, nonvolatile magnetic media, a magnetic disk drive that reads from or writes to a removable, nonvolatile magnetic disk, an optical disk drive that reads from or writes to a removable, nonvolatile optical disk such as a CD ROM or other optical media. Other removable/non-removable, volatile/nonvolatile computer storage media that can be used in the exemplary operating environment include, but are not limited to, magnetic tape cassettes, flash memory cards, digital versatile disks, digital video tape, solid state RAM, solid state ROM, and the like.

The computer may operate in a networked environment via connections to one or more remote computers. The remote computer may comprise a personal computer (PC), server, router, network PC, peer device or other common network node, or another quantum computer, and typically includes many or all of the elements described supra. Such networking environments are commonplace in offices, enterprise-wide computer networks, intranets and the Internet.

When used in a LAN networking environment, the computer is connected to the LAN via network interface 76. When used in a WAN networking environment, the computer includes a modem or other means for establishing communications over the WAN, such as the Internet. The modem, which may be internal or external, is connected to the system bus via user input interface, or other appropriate mechanism.

Computer program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++, C# or the like, conventional procedural programming languages, such as the “C” programming language, and functional programming languages such as Python, Hotlab, Prolog and Lisp, machine code, assembler or any other suitable programming languages.

Also shown in FIG. 1 is the optional data feedback loop between the quantum processing unit 38 and the external support unit 12 provided by the partial quantum data read out. The quantum state is stored in the qubits of the one or more quantum cores 60. The detectors 62 function to measure/collapse/detect some of the qubits and provide a measured signal through appropriate buffering to the output ADC block 74. The resulting digitized signal is sent to the decision logic block 16 of the external support unit 12 which functions to reinject the read out data back into the quantum state through the high speed interface 58 and quantum initialization circuits. In an alternative embodiment, the output of the ADC is fed back to the input of the QPU.

In one embodiment, quantum error correction (QEC) is performed via QEC block 64 to ensure no errors corrupt the read out data that is reinjected into the overall quantum state. Errors may occur in quantum circuits due to noise or inaccuracies similarly to classic circuits. Periodic partial reading of the quantum state function to refresh all the qubits in time such that they maintain their accuracy for relatively long time intervals and allow the complex computations required by a quantum computing machine.

It is appreciated that the architecture disclosed herein can be implemented in numerous types of quantum computing machines. Examples include semiconductor quantum computers, superconducting quantum computers, magnetic resonance quantum computers, optical quantum computers, etc. Further, the qubits used by the quantum computers can have any nature, including charge qubits, spin qubits, hybrid spin-charge qubits, etc.

In one embodiment, the quantum structure disclosed herein is operative to process a single particle at a time. In this case, the particle can be in a state of quantum superposition, i.e. distributed between two or more locations or charge qdots. In an alternative embodiment, the quantum structure processes two or more particles at the same time that have related spins. In such a structure, the entanglement between two or more particles could be realized. Complex quantum computations can be realized with such a quantum interaction gate/structure or circuit.

In alternative embodiments, the quantum structure processes (1) two or more particles at the same time having opposite spin, or (2) two or more particles having opposite spins but in different or alternate operation cycles at different times. In the latter embodiment, detection is performed for each spin type separately.

A high level block diagram illustrating a generalized quantum structure interfaced to classical integrated electronic control circuitry is shown in FIG. 2. The example quantum circuit, generally referenced 80, comprises quantum structure 84 at its core, and support circuitry that in one embodiment is integrated on the same physical realized support or external on a different physical realized support. The support circuitry comprises reset circuits 82 for flushing the quantum structure of any available free carriers before starting the quantum operation and to prepare it for a new quantum operation, injector circuits 88 that function to inject one or more particles into the quantum core structure, imposer circuits 90 that control the quantum operation and the flow of the quantum computation between the injected particles, detector circuits 86 that sense whether a particle is present or not in the output qdots and the particles at the output points of the quantum structure after the quantum operation has been performed, and control circuitry 92. Note that in one embodiment, multiple such quantum structures/quantum cores can be interconnected and/or operated in parallel. Further note that the common electrical node of the reset circuit 82 output and the injector circuit 88 output can be the same as the electrical node of the detector circuit (86) input. In this case, the three circuits time-share their active operations.

To achieve quantum operation, physical structures must be cooled to cryogenic temperatures and be isolated as much as possible from environmental perturbations (e.g., external electric fields and/or magnetic fields, etc.). To perform quantum computing using particles in a semiconductor structure, the particles (e.g., electrons, holes, etc.) need to be able to be excited in quantum states and to stay in such states for a long enough time for the operation and measurement of the quantum operation to be realized. At higher temperatures, the thermal energy of the particle results in the decoherence of its quantum state.

In one embodiment, the semiconductor based quantum structure uses a continuous well with an imposing gate that generates a controlled local depletion region to separate two or more regions of the well that form quantum dots (qdots). By modulating the potential of the imposer gate, controlled tunneling through the local depleted region is enabled between the plurality of sections of the continuous well, realizing the function of a position/charge qubit. It is appreciated that more complex structures having a higher number of qdots per continuous well and a larger number of wells can be built using the techniques of the present invention. Both planar and 3D semiconductor processes can be used to build such well-to-well tunneling quantum structures. By combining a number of such elementary quantum structures/gates, a quantum computing machine is realized.

Quantum Operation

To aid in understanding the principles of the present invention, a brief explanation of quantum operation is presented below.

As stated supra, in classic electronics, the unit of information is a bit that can represent only one of the two states “0” and “1” at a given time. Computations in classical computers are performed sequentially and every bit can hold only one state at a time.

As stated supra, quantum electronics uses the quantum behavior of particles to perform computations. The unit of quantum information is a quantum bit or qubit. A qubit has two or more base states denoted by 0 and 1 (or |0> and |1>) but in contrast with a classic bit, a qubit can be in a superposed state that contains some percentage ‘a’ of state {circumflex over (0)}, and some percentage ‘b’ of state {circumflex over (1)}, denoted by a{tilde over (0)}+b{circumflex over (1)}. Since a qubit in quantum structures can simultaneously be in multiple superposed states, multiple sets of computations can be performed concurrently, resulting in large quantum computation speed-ups, when compared with classic computations.

A quantum particle is described by its position and/or spin. The particles used in quantum structures are called quantum particles. There are qubits based on the quantum position of the particles, also named charge-qubits, while other qubits use the spin of the quantum particles, also named spin-qubits. In quantum structures, the charge carriers are held in specific regions called quantum dots or qdots. A quantum structure is constructed from one or more qdots.

Performing a quantum computation involves several steps. First the structure needs to be reset, which means that all the free carriers (e.g., electrons or holes) from the structure need to be flushed out. Once the free carriers are removed, the structure is initialized meaning particles are introduced in one of the base states (e.g., 0 or 1). In the case of a charge-qubit (position-qubit) it means that a carrier is loaded in one of the qdots. A free carrier not coming from the quantum initialization process can interact with the quantum particles and result in decoherence, i.e. loss of quantum information. After the particles have been loaded in the corresponding base states they undergo the desired quantum operation under control of gate control terminals. Once the desired quantum operations are complete a detection is performed whereby the presence or absence of a particle in a given qdot at a given time is tested. Detection is usually destructive which means that the quantum particle's wavefunction and its state collapse. Special nondestructive detection/measurement exist that do not collapse the quantum state. In such cases, multiple measurements of the same quantum state can be performed.

The position of a quantum particle is given by the region where the particle wave-function is mostly present. In one embodiment, quantum structures use semiconductor qdots realized with semiconductor wells where the particle transport is done through tunneling which is a quantum effect. The tunneling or particle transport is controlled by control terminals. In one embodiment, the control terminals are realized using gates but they may comprise other semiconductor process layers.

To illustrate, consider a generic position double qdot structure having a “dog bone” shape shown in FIG. 3A. The structure comprises a control gate 974 giving rise to two qdots 970, 972, that correspond to the |0> and |1> base states, or “left” and “right” base states, when an electrostatic particle happens to be there. Higher order position quantum structures can be realized having more than two base states and thus use more than two qdots. The particle transport from one qdot to the other is done through tunneling. Before initialization both qdots must be cleared of quantum particles since a reset flushes out all free carriers.

Note that a key difference between the classic and quantum structures/circuits is that the structure can not only be in the base states |0> and |1>, but also in a superposed position a|0>+b|1>, with a constraint |a|²+|b|²=1, meaning the particle is present simultaneously in both qdots of the structure. When the signal on the control terminal causes a lowering of the tunneling barrier, the particle initially loaded in the left qdot 970 will tunnel to the right qdot 972. The position of the particle and thus the corresponding quantum state is given by the pulse width of the signal V_(control) applied to the control gate. If the pulse width is long enough, after the particle has tunneled to the right qdot 972 it will tunnel back to the left qdot 970 and then again to the right qdot 972 and the process repeats itself in an oscillatory fashion. The period of this oscillation, called the Rabi oscillation (especially in case of a time-dependent Hamiltonian), depends on the tunnel current and thus on the control signal V_(control) applied and the configuration and process of the specific structure. The time needed for a particle to tunnel forward and then back to its initial position is called the Rabi period.

The Rabi oscillation after reset but before initialization is shown in FIG. 3B where waveform 976 represents an ideal oscillation and waveform 978 represents oscillation with some amount of decoherence or leakage of wavefunction.

Consider a quantum particle 976 loaded in the left qdot 970 with a base state |0>, as shown in FIG. 3C. The Rabi oscillation waveform at initialization (dot referenced 980) is shown in FIG. 3D. In a horizontally oriented double qdot, a quantum particle 976 loaded in the right qdot 972 is considered in the base state |1>, as shown in FIG. 3E. Similarly, the up and down qdots correspond to the |0> and |1> base states in a vertically oriented double qdot. The control terminal (typically the gate) determines the height of the tunnel barrier. If the potential barrier is high then tunneling is blocked (i.e. negligible). On the other hand, if the potential barrier is low then tunneling is allowed and the particle moves from one qdot to the other, resulting in a change in quantum state.

If the control signal pulse width is equal to half the Rabi period as shown in FIG. 3F, then the particle will tunnel from the left qdot 970 to the right qdot 972, i.e. transition from the |0> base state to the |1> base state also known as a quantum inversion, trajectory of which is represented by waveform solid portion 982.

If the control pulse width is equal to one quarter of the Rabi period as represented by waveform solid portion 984 trajectory in FIG. 3H, then the particle will be present equally in the left qdot 970 and in the right qdot 972 as shown in FIG. 3G. This equal distribution quantum state is called the Hadamard state and is fundamental for quantum computation. The double qdot with a quarter Rabi period control signal performs the function of a fundamental Hadamard quantum gate. Considering the sinewave of an oscillatory effect, the Hadamard state corresponds to the zero crossings, while the peak of the positive cycle corresponds to the base state |0> and the peak of the negative cycle corresponds to the base state |1>. All points between the positive and negative peaks correspond to superposition states.

If the pulse width of the control signal is less than one quarter the Rabi period as represented by solid waveform portion 986 in FIG. 3J, then the quantum particle is split between the two qdots as shown in FIG. 3I but it will have a larger presence in the left qdot 970 versus the right qdot 972. Similarly, if the pulse width is larger than one quarter the Rabi period as represented by solid waveform portion 988 in FIG. 3L, than the quantum particle is split as shown in FIG. 3K but will have a larger presence in the right qdot 972.

If the position of the particle is represented as a vector of constant length in a circular coordinate system, a vector pointing up represents the |0> base state, while a vector pointing down represents the |1> base state. Any other position is a superposed state that constitutes a quantum rotation operation. As such the double qdot quantum structure with a variable control signal pulse width constitutes a controlled quantum rotation gate.

The initialization of a quantum structure is realized by an interface device (described in more detail infra) having one side connected to classical circuitry and the other side connected to quantum circuitry, i.e. half classic, half quantum. On the classic side, the carriers (e.g., electrons or holes) have a collective behavior, sometimes called a sea of electrons (or holes). On the quantum side, the carriers exhibit single charge carrier or a few carrier behavior and their interaction is based on the laws of quantum mechanics. Injecting exactly a single particle in the quantum structure at a given qdot can be realized through the tunneling effect in the interface device. Once a single particle has tunneled, the electric field changes such that it opposes the tunneling of a subsequent particle. Such behavior of the interface device is critical to be able to inject one or multiple single particles into one or multiple qdots of a given quantum structure.

The pulse width of the control signals can be digitally controlled on the classical side of the circuits and thus determine what kind of quantum operation is performed, resulting in a programmable quantum machine. In this case, the same hardware implementation is able to perform different quantum operations based on the specific control signal applied.

Note that each quantum particle injected into the quantum structure represents a qubit. In the position qubit at least two qdots are needed to implement a qubit. In the general case, structures with N qubits and M qdots can be constructed. The number of injectors, however, should be equal to N if all particles are injected at the same time, or it can be lower than N if the particles are injected at different times.

A diagram illustrating a circular shaped semiconductor quantum structure incorporating local depleted well tunneling is shown in FIG. 4A. The quantum structure, generally referenced 100, comprises a continuous well with a local depleted region with a control gate 106 fabricated over it that functions to separate the well into two or more portions each implementing a qdot. In this example, the continuous well is split into two qdots 102, 104 with a tunneling path 108 formed between them for the quantum particle 110, e.g., electron, to tunnel through. The tunneling path 108 is considered to effectively connect the two wells 102 and 104 in a quantum manner. The quantum operation is controlled by the gate 106 fabricated over the tunneling path 108. The gate functions to modulate the energy barrier created by the local depleted region. The two sections of the well, the tunneling path with the local depleted region, and the control gate can take any number of different shapes (described infra) allowed by the particular semiconductor process used (planar or 3D).

In one embodiment, the two qdots 102, 104 are linked by a region 108 that is partially or completely locally depleted and in which tunneling occurs as indicated by arrow 109 through the tunneling path. The control gate typically overlaps the tunneling path in order to maintain well-controlled depletion of the entire linking region between the two qdots. This prevents direct electric conduction between the two qdots.

The depletion region is required for quantum operation of the structure. If there were no depletion region, the operation would revert to a classical transistor operation in on/off modes and the particle can normally move from one side to the other. Note that the probability of a particle tunneling through the depletion region is approximately exponentially linked to the width of the depletion region. If the depletion region is very narrow, the particle will tunnel and the quantum operation is achieved. If the depletion region is wide, then there is no tunneling or the tunneling is so weak that it can be neglected. This is also dependent on the tunneling barrier height. For a p-type semiconductor material, placing a positive potential on the gate will repel the holes and create a depletion region. Note that the voltage is necessarily lower than the level that results in the creation of an inversion channel.

The control signals that need to be applied to the gate depend on whether the semiconductor material is p or n type. Consider for example p-type semiconductor material, with no potential on the gate, the particle may be free to tunnel. Placing a positive potential on the gate will repel the particles (i.e. holes) and create the depletion region thereby hindering tunneling. If the potential on the gate is removed or brought closer to zero to zero or made negative, the particles are permitted to tunnel in relation to the potential applied. The operation of the quantum structure is significantly different than that of a conventional transistor.

In one embodiment, the two qdots 102, 104 are realized by a single semiconductor well having a polysilicon gate on top. The tunneling happens laterally or horizontally through the depleted region that isolates the two qdots.

Note also that in one embodiment the well is surrounded by oxide, isolating layers, and/or one or more wide depletion regions that prevent the quantum particle from escaping from the well.

A diagram illustrating the change in the aperture tunnel barrier from a wide depletion region to a narrow depletion region is shown in FIG. 4B. To contain or trap the quantum particle 114, the barrier potential 112 between the two wells is made high (dashed line 116). Lowering the barrier potential between the two wells (solid line below the dashed line) enables the quantum particle to tunnel from one qdot to the other.

A diagram illustrating a first rectangular shaped semiconductor quantum structure incorporating local depleted well tunneling is shown in FIG. 4C. The quantum structure, generally referenced 120, is similar to structure 100 of FIG. 4A apart from the dog bone shape of the continuous local depleted well. Control gate 126 is fabricated over the well and functions to separate the well into two qdots 122, 124 with tunneling path 128 formed between them for the quantum particle 130 to tunnel through. The quantum operation is controlled by the gate 126 fabricated over the tunneling path 128. The gate functions to modulate the barrier created by the local depleted region.

The two qdots 122, 124 are linked by a region 128 that is partially or completely locally depleted and in which tunneling occurs as indicated by arrow 129 through the tunneling path. The control gate typically overlaps the tunneling path in order to maintain well-controlled depletion of the entire linking region between the two Qdots. This prevents direct electric conduction between the two qdots.

A diagram illustrating the change in the aperture tunnel barrier from a wide depletion region to a narrow depletion region is shown in FIG. 4D. To contain or trap the quantum particle 134, the barrier potential 132 between the two wells is made high (dashed line 136). Lowering the barrier potential (solid line) enables the quantum particle to tunnel from one qdot to the other.

A diagram illustrating a second rectangular shaped semiconductor quantum structure incorporating local depleted well tunneling is shown in FIG. 5. The quantum structure, generally referenced 140, is similar to structure 100 of FIG. 4A apart from the ‘S’ shape of the continuous well with local depleted region. Control gate 146 is fabricated over the well and functions to separate the well into two qdots 142, 144 with tunneling path 148 formed between them for the quantum particle 149 to tunnel through. The quantum operation is controlled by the gate 146 fabricated over the tunneling path 148. The gate functions to modulate the barrier created by the local depleted region.

The two qdots 142, 144 are linked by a region 148 that is partially or completely locally depleted and in which tunneling occurs as indicated by arrow 147 through the tunneling path. The control gate typically overlaps the tunneling path in order to maintain well-controlled depletion of the entire linking region between the two Qdots. This prevents direct electric conduction between the two qdots.

A diagram illustrating a cross section of an example semiconductor quantum structure 150 is shown in FIG. 6. An exemplary cross section in a silicon-on-insulator (SOI) process is shown in which the substrate 152 is low doped (i.e. high resistivity) and is isolated from the quantum device with a buried oxide layer (BOX) 154. This reduces the decoherence of the quantum particle. In one embodiment, the semiconductor quantum device employs tunneling through the local depleted region. In another embodiment, tunneling occurs through the oxide layer between the semiconductor well 160 (low doped or undoped) and the partially overlapping gate 158 and oxide layer 166. The active layer 160 is isolated using oxide from adjacent structures, e.g., shallow trench isolation (STI) 156, reducing further the quantum particle decoherence.

Note that the substrate may comprise (1) a semiconductor, (2) silicon on insulator (SOI) substrate, where the substrate comprises sapphire, glass, organic material, etc., (3) an insulating substrate replacement, for example, sapphire, glass, organic material, plastic, polymer, etc., or (4) any other insulating material compatible with a semiconductor process.

Note that regardless of the substrate used, the quantum structure must be electrically isolated from the substrate for the structure to operate properly. Otherwise, the quantum particle may escape thus preventing quantum operation of the structure.

Several ways to electrically isolate the quantum structure include: (1) utilizing an SOI or low doped substrate where the oxide layer electrically isolates the quantum structure from the substrate; (2) using substrate replacement such as an insulator material, e.g., polymer, glass, etc.; and (3) using a fixed depletion region, as the quantum particle can tunnel only through a relatively narrow insulating region such as very thin oxide or a thin depletion region. If the depletion region is too wide, the quantum particle is prevented from traveling. Note that this last option can be fabricated using bulk processes.

The quantum operation is controlled by the gate located over the tunneling path that modulates the barrier created by the local depletion region.

In one embodiment, a low doped substrate interacts with the quantum particle with far and weak interactions. Tunneling of the quantum particle 162 occurs in region 164 between the two qdots formed in the active layer 160 and the tunnel path may be straight through from one qdot to the other (see dashed arrow 168) or may take a path through the gate and back to the active layer (see dashed arrow 169). Alternatively, the substrate may comprise a substrate replacement that includes non-conducting material, e.g., polymer, glass, sapphire, without free charge or ions that can interact with the quantum particle.

In both cases, the active well is preferably isolated on all sides (i.e. typically with oxide) where the particles are permitted to travel only through a narrow link where tunneling occurs.

Alternatively, bulk semiconductor processes are used where the substrate 152 is isolated from the quantum device using a large depleted region under the quantum gate instead of BOX. In another alternative embodiment, the quantum device is placed directly into the substrate. The quantum device can be isolated laterally from other devices using oxide layers 156 (e.g., STI or another preferably low doped well). In another alternative embodiment, a bulk semiconductor quantum structure replaces the substrate with an isolator material 152 having no free carriers or ions that can interact with the quantum particle. In an alternative embodiment, a substrate replacement process or a semiconductor on insulator process can also be used.

The cross section 150 shows the quantum structure with well-to-well tunneling through the local depleted region. It is noted that if the depleted region 164 is wide, then no or negligible tunneling 168 is present. If under the control of the gate the tunneling barrier is lowered and the depletion region gets narrower, a sizeable tunneling current may occur, resulting in the quantum particle tunneling from one qdot to the other.

Note that tunneling is also possible from the well to the gate and then from the gate to the adjacent well, bypassing the local depleted area (arrow 169). The width of the depleted area, however, can be made narrower than the thin gate oxide and thus the predominant tunneling can be made to be through the local depleted region.

In some cases, the gate oxide thickness is reduced using special materials such as hafnium oxide. The tunneling barrier height, however, is still high and tunneling is likely to happen through the depletion layer.

In accordance with the present invention, the quantum structure may comprise numerous shapes and sizes constrained only by design rule check (DRC) of the particular semiconductor process used to fabricate the structure. Several examples of quantum structure shapes, e.g., circles, squares, rectangles, polygons, etc. will now be described. In each case, these shapes can be used for the constituent layers and for one or more qdots making up the quantum structure.

A double qdot quantum structure which is the elementary structure for position qubit quantum computing contains two quantum dots and a tunneling path (often narrow) between them.

Quantum Structure Shapes

A diagram illustrating an example circular shape 170 for the quantum structure of the present invention is shown in FIG. 7A. A diagram illustrating an example square shape 172 for the quantum structure of the present invention is shown in FIG. 7B. A diagram illustrating an example square shape with rounded corners 174 for the quantum structure of the present invention is shown in FIG. 7C. A diagram illustrating an example hexagonal shape 176 for the quantum structure of the present invention is shown in FIG. 7D. A diagram illustrating an example rectangular shape 178 for the quantum structure of the present invention is shown in FIG. 7E.

A diagram illustrating an example trapezoidal shape 180 for the quantum structure of the present invention is shown in FIG. 7F. A diagram illustrating a first example overlapping square shape 182 for the quantum structure of the present invention is shown in FIG. 7G. A diagram illustrating a first example ‘L’ shape 184 for the quantum structure of the present invention is shown in FIG. 7H. A diagram illustrating an example ‘S’ shape 186 for the quantum structure of the present invention is shown in FIG. 7I. A diagram illustrating a second example ‘L’ shape 188 for the quantum structure of the present invention is shown in FIG. 7J.

A diagram illustrating an example barely touching squares shape 189 for the quantum structure of the present invention is shown in FIG. 7K. Note that in this example shape and others it is preferable that the squares overlap as little as possible since it is desirable to have as narrow a tunneling region as possible to maximize control. A large tunneling area is more difficult to control and to deplete sufficiently to prevent partial or complete tunneling.

A diagram illustrating an example barely touching square shape 190 with optical proximity control 192 for the quantum structure of the present invention is shown in FIG. 7L. A diagram illustrating an example double squares 194 with narrow neck 196 shape for the quantum structure of the present invention is shown in FIG. 7M. A diagram illustrating a second example overlapping square shape 198 for the quantum structure of the present invention is shown in FIG. 7N. A diagram illustrating a third example overlapping square shape 200 for the quantum structure of the present invention is shown in FIG. 7O.

A diagram illustrating an example barely touching rectangular shape 202 for the quantum structure of the present invention is shown in FIG. 7P. A diagram illustrating an example barely touching double overlapping squares shape 222 for the quantum structure of the present invention is shown in FIG. 7Q. A diagram illustrating an example double squares connected via single smaller square shape 208 for the quantum structure of the present invention is shown in FIG. 7R. A diagram illustrating an example double squares connected via double smaller squares shape 204 for the quantum structure of the present invention is shown in FIG. 7S.

Several alternative ways of imposing the potential on the control gate will now be described. For illustration purposes only, double overlapping square shapes are used for the qdots. It is appreciated that other shapes may be used with each technique without departing from the scope of the invention. Note that the width of the tunneling section of the continuous well in each case is preferably as small as possible, but can vary in size based on the given DRC of the semiconductor process used.

Control Gate

A diagram illustrating a first example control gate for the quantum structure of the present invention is shown in FIG. 8A. The quantum structure, generally referenced 220, comprises a floating control gate 226 with an adjacent gate 222 that is in close proximity thereto that imposes potential to the gate 226 of the double overlapping square shaped qdots 224 with tunnel path 228. Note that changing the potential of the overlapping control gate is operative to modulate the tunnel barrier height.

A diagram illustrating a second example control gate for the quantum structure of the present invention is shown in FIG. 8B. The quantum structure, generally referenced 230, comprises a metal control gate 232 imposing on the floating control gate 234 using adjacent or overlap positioning over the control gate 234 of the double overlapping square shaped qdots 236 with tunnel path 238.

A diagram illustrating a third example control gate for the quantum structure of the present invention is shown in FIG. 8C. The quantum structure, generally referenced 240, comprises a contact 244 from a metal feed 242 to a control gate 246 over double overlapping square shaped qdots 248 with tunnel path 249. The control gate is driven directly with an electrical signal (e.g., pulsed electric signal).

Quantum Structures With Control Gates

As described supra, the quantum structure may comprise numerous shapes and sizes constrained only by design rule check (DRC) of the particular semiconductor process used to fabricate the structure. Several examples of quantum structures having one or more control gates will now be described. It is important to note that there is a difference between the shapes drawn in the figures and the physical realized shapes. Further, several factors such as the semiconductor process used contribute to determining the physical shapes realized. Note also that in most cases, the link channel is mandatory for the quantum structures employing tunneling through the depletion region. The link channel, however, may not be present on the layers drawn in the figures.

Each semiconductor quantum structure disclosed uses well-to-well tunneling through a local depleted region. In order to exercise good control over the tunneling effect, the tunneling path section of the well is preferably relatively narrow when compared with the dimensions of the rest of the well that constitutes the qdots. A gate is placed on top of the tunneling path section of the well in which the local depleted region is induced. A complete overlap of the control gate on the tunneling path is preferable in order to have good control over the entire width of the tunneling path and achieve reliable isolation between the two or more sections of the continuous well that implements the quantum dots. The potential on the control gate functions to modulate the width of the local depletion region and to control the tunneling between the two adjacent sections of the well that represent two separate qdots (i.e. well-to-well tunneling). As described supra, this potential is imposed, for example, by another metal layer with no contact to gate 226 (i.e. a floating gate) as shown in FIG. 8A or with a metal layer contacted to the gate (i.e. directly driven gate) as shown in FIG. 8C. The overlapping gate is positioned such that a smaller overlap with the two adjacent sections of the well is realized resulting in a larger Coulomb blockade voltage.

A diagram illustrating an example quantum structure with double square corner touching shape is shown in FIG. 9A. The quantum structure, generally referenced 250, comprises a continuous well with control gate 254 placed over edge portions 251, 253 of the square shapes to form two qdot regions 252.

A diagram illustrating an example quantum structure with double square shape and optical proximity control is shown in FIG. 9B. The quantum structure, generally referenced 260, comprises a continuous well with control gate 264 placed over edge portions of the square shapes to form two qdot regions 262. Optical proximity control 266 is used to improve the tunnel path. As is known in the semiconductor processing arts, optical proximity correction can be used within the vicinity of the local depleted tunneling well to aid in improving the resulting structures fabricated on the substrate. Note that optical proximity correction techniques may be used with any of the structures disclosed in this document to improve the resulting structures. Note that the squares 266 shown only exist on one or more masks used in the fabrication of the structure and do not reflect any structures actually built on the substrate. These squares, however, typically have an effect on the shape of such structures constructed nearby. The desired effects include width and length adjustments of the tunneling path.

Note that in general, nanometer semiconductor processes natively yield distortions around corners and the narrow features. Optical correction helps realize physical shapes close to the desired shapes.

A diagram illustrating an example quantum structure with double square and narrow neck shape is shown in FIG. 9C. The quantum structure, generally referenced 270, comprises a continuous well with control gate 274 placed over narrow tunnel path 276 and edge portions of the square shapes to form two qdot regions 272.

A diagram illustrating a first example quantum structure with double overlapping square shape is shown in FIG. 9D. The quantum structure, generally referenced 280, comprises a continuous well with control gate 284 placed over narrow tunnel path 286 (but wider than tunnel path 296 in FIG. 9E) and edge portions of the square shapes to form two qdot regions 282.

A diagram illustrating a second example quantum structure with double overlapping square shape is shown in FIG. 9E. The quantum structure, generally referenced 290, comprises a continuous well with control gate 294 placed over narrow tunnel path 296 and edge portions of the square shapes to form two qdot regions 292.

A diagram illustrating an example quantum structure with shape is shown in FIG. 9F. The quantum structure, generally referenced 300, comprises a continuous well with control gate 304 placed over the transition portion of the rectangular shapes to form two qdot regions 302.

A diagram illustrating an example quantum structure with double rounded barely touching square shape is shown in FIG. 9G. The quantum structure, generally referenced 310, comprises a continuous well with control gate 314 placed over narrow tunnel path 316 and edge portions of the rounded square shapes to form two qdot regions 312.

A diagram illustrating an example quantum structure with double rectangular shape is shown in FIG. 9H. The quantum structure, generally referenced 320, comprises a continuous well with control gate 324 placed over narrow tunnel path 326 and edge portions of the rectangular shapes to form two qdot regions 322.

A diagram illustrating an example quantum structure with double square connected via double smaller square shape is shown in FIG. 9I. Optical proximity correction is used here to turn the small feature connecting shapes into a narrow continuous link channel. The quantum structure, generally referenced 330, comprises a continuous well with control gate 334 placed over double small square tunnel path 336 and edge portions of the square shapes to form two qdot regions 332.

A diagram illustrating an example quantum structure with double rounded square with narrow neck shape is shown in FIG. 9J. The quantum structure, generally referenced 340, comprises a continuous well with control gate 344 placed over contoured narrow tunnel path 346 and edge portions of the rounded square shapes to form two qdot regions 342.

A diagram illustrating an example quantum structure with an overlapping pair of double rounded squares with narrow neck shape is shown in FIG. 9K. The quantum structure, generally referenced 350, comprises a continuous well with two control gates 354 placed over a contoured narrow tunnel path 356 and edge portions of the rounded square shapes to form three qdot regions 352. Note that the middle qdot is longer, being comprised of two semiconductor squares.

A diagram illustrating a first example quantum structure with a pair of barely touching double overlapping square shape is shown in FIG. 9L. The quantum structure, generally referenced 360, comprises a continuous well with control gate 364 placed over tunnel path 366 and edge portions of the double square shapes to form two qdot regions 362.

A diagram illustrating a second example quantum structure with a pair of double corner overlapping square shape is shown in FIG. 9M. The quantum structure, generally referenced 370, comprises a continuous well with two floating control gates 374 with adjacent imposing gate potential placed over tunnel paths 378 and edge portions of the square shapes to form three qdot regions 372. Note that the middle qdot is formed by two squares of active silicon.

A diagram illustrating a first example quantum structure with a double square shape with narrow neck and butterfly shaped control gate is shown in FIG. 9N. Note that most of the quantum structures described supra comprise square or rectangular shaped gates. Some available semiconductor processes, however, allow for composed shapes for the gate. In these cases, both the well and the gate have a narrow connecting channel. The quantum structure, generally referenced 380, comprises a continuous well with control gate 382 placed over narrow tunnel path 386 to form two qdot regions 384. Here, the gate and the well both have narrow connecting channels. This structure results in a much smaller gate to well overlap resulting in a much higher Coulomb blockade voltage for the structure. This enables a higher performance of the quantum structure since a larger signal to noise ratio is achieved.

A diagram illustrating a second example quantum structure with a double square shape with narrow neck and butterfly shaped control gate is shown in FIG. 9O. Similar to the structure of FIG. 9N, the quantum structure, generally referenced 390, comprises a continuous well with control gate 392 placed over contoured narrow necked tunnel path 396 to form two rounded square qdot regions 392. Here too, the gate and the well both have narrow connecting channels.

A diagram illustrating an example quantum structure with a pair of overlapping double square shapes with narrow neck and butterfly shaped control gates is shown in FIG. 9P. The quantum structure, generally referenced 400, comprises a continuous well with two floating control gates 402 electrostatically coupled to adjacent imposing gates 406 placed over contoured narrow necked tunnel paths 408 to form three rounded square qdot regions 404 with the gates 406 and the wells having narrow connecting channels.

A diagram illustrating an example conventional field effect transistor (FET) with drain and source doped diffusion and contacts is shown in FIG. 9Q. Using a conventional field effect transistor (FET) structure to build semiconductor quantum structures results in significantly degraded performance. In one embodiment, a modified semiconductor process is used to construct optimized semiconductor quantum structures.

Conventional wells have rectangular shapes disposed parallel to each other. In one embodiment, the quantum structure uses (1) staircase well shapes that provide pairs of locations where the interaction between quantum particles/states is very strong and (2) other pairs of locations that have weak or negligible interaction between the particles situated at those locations.

The conventional FET structure, generally referenced 410, comprises drain and source doped diffusion with contacts 412 with metal on top, and gate 416 with contacts 414. This structure results in significantly higher parasitic gate capacitance since it includes the gate-to-metal, gate-to-contact and gate-to diffusion additional components. Note that in classic FET structures, carriers move either through drift under an external electric field or through diffusion due to a gradient of concentration. An inversion channel is created by a relatively large gate voltage.

A diagram illustrating an example half conventional FET and half (potentially) quantum structure is shown in FIG. 9R. In accordance with the present invention, a modified semiconductor process enables an active layer without any diffusion, contact and metal on top. The structure, generally referenced 420, comprises a conventional doped side 422 with diffusion contacts, an undoped or lightly doped quantum side 426, and gate 427 with contacts 424. Such a structure has a half-classic, half-quantum structure with one side of the gate without any n or p doping and without contacts. This type of device can be used, for example, at the interface between classic circuits and quantum circuits. In this case, the carriers move through tunneling from the classic side to the quantum side.

A diagram illustrating an example quantum structure with rectangular shaped wells is shown in FIG. 9S. The full quantum structure, generally referenced 430, does not have any n or p doping or contacts on either side. Both sides 432 of the gate 436 with contacts 434 have the same active layer width which is approximately equal to the gate width. This results in a larger gate capacitance. To reduce the parasitic gate capacitance, the width of the active layer may be made smaller than the gate width on one or both sides.

A diagram illustrating an example quantum structure with dissimilar rectangular shaped wells is shown in FIG. 9T. The structure, generally referenced 440, comprises an asymmetric aperture tunneling well with gate 446 and gate contacts 448 placed thereover to generate two qdots 442, 444 with reduced parasitic capacitance on the right side qdot.

A diagram illustrating an example quantum structure with offset rectangular shaped wells is shown in FIG. 9U. The structure, generally referenced 450, comprises an asymmetric aperture tunneling well with gate 456 and gate contacts 458 placed thereover to generate two qdots 452, 454 with both qdots having reduced parasitic capacitance.

Using active wells having different widths on the both sides of the gate reduces the parasitic gate capacitance. A more significant reduction in gate capacitance can be achieved, however, by having an active well structure having a narrow region under the gate and wider regions on either side of the gate.

A diagram illustrating a first example quantum structure with spaced apart rectangular shaped wells is shown in FIG. 9V. The structure, generally referenced 460, comprises a symmetric dog bone aperture tunneling well with gate 466 having gate contacts 468 placed thereover to generate two qdots 462, 464 with reduced parasitic capacitance on both sides. Note, however, that there remains a residual overlap of the gate and the wider active wells on the two sides of the gate. Note that the aperture refers to the narrowed link channel between the two wider well regions.

A diagram illustrating a first example quantum structure with spaced apart rectangular shaped wells offset from each other is shown in FIG. 9W. The structure, generally referenced 470, comprises an asymmetric dog bone aperture tunneling well with gate 476 and gate contacts 478 placed thereover to generate two qdots 472, 474 with reduced parasitic capacitance on both sides. Note, however, that there remains a residual overlap of the gate and the wider active wells on the two sides of the gate.

In one embodiment, to further reduce gate capacitance the overlap between the gate and the wider wells on the sides are eliminated. A diagram illustrating a second example quantum structure with spaced apart rectangular shaped wells is shown in FIG. 9X. The structure, generally referenced 480, comprises a symmetric dog bone aperture tunneling well with gate 486 and gate contacts 488 placed thereover to generate two qdots 482, 484 with reduced parasitic capacitance on both sides and no well-gate overlap in the wider regions.

A diagram illustrating a second example quantum structure with spaced apart rectangular shaped wells offset from each other is shown in FIG. 9Y. The structure, generally referenced 490, comprises an asymmetric dog bone aperture tunneling well with gate 496 and gate contacts 498 placed thereover to generate two qdots 492, 494 with reduced parasitic capacitance on both sides and no well-gate overlap in the wider regions.

As described supra, the quantum structure may be symmetric or asymmetric. The “dog-bone” quantum structure has some overhang of the wider wells passed the edge of the narrow link. The asymmetric dog bone quantum structure does not have any overhang on the narrow link side. A diagram illustrating a third example quantum structure with spaced apart rectangular shaped wells offset from each other is shown in FIG. 9Z. The structure, generally referenced 500, comprises an asymmetric dog bone aperture tunneling well with partial overlap of the gate on the wide wells and overhang passed the narrow link edges, and with gate 506 and gate contacts 508 placed thereover to generate two qdots 502, 504.

A diagram illustrating a fourth example quantum structure with spaced apart rectangular shaped wells offset from each other is shown in FIG. 9AA. The structure, generally referenced 510, comprises an asymmetric dog bone aperture tunneling well with partial overlap of the gate on the wide wells and overhang passed the narrow link edges, and with gate 516 and gate contacts 518 placed thereover to generate two qdots 512, 514 with increased gate to well capacitance, but which may ease the fabrication process.

Narrow links between the two wider wells may be realized without having them drawn as such. In one embodiment, two wells have a punctual drawn contact but during fabrication a narrow link channel is formed between the two wells using optical proximity correction. A diagram illustrating a first example quantum structure with corner abutting rectangular shaped wells is shown in FIG. 9AB. The structure, generally referenced 520, comprises an aperture tunneling well with punctual drawn link between the two wells, and with gate 526 and contacts 528 placed thereover to generate two qdots 522, 524.

A diagram illustrating a second example quantum structure with corner abutting rectangular shaped wells is shown in FIG. 9AC. The structure, generally referenced 530, comprises the physical realization of the structure of FIG. 9AB with a narrow link channel formed between the two wells using a suitable technique such as optical proximity correction channel, and with gate 536 and contacts 538 placed thereover to generate two qdots 532, 534.

Note that it is not mandatory that the two wide wells have a punctual contact in order to obtain a narrow link channel between them. In some cases, it is sufficient that they are placed in very close proximity, and optical proximity correction results in a link channel in the physically realized shapes.

A diagram illustrating a third example quantum structure with corner abutting rectangular shaped wells is shown in FIG. 9AD. The structure, generally referenced 540, comprises an aperture tunneling well without contact between the two wells but in very close proximity, and with gate 546 and contacts 548 placed thereover to generate two qdots 542, 544.

A diagram illustrating a fourth example quantum structure with corner abutting rectangular shaped wells is shown in FIG. 9AE. The structure, generally referenced 550, comprises the physical realization of the structure of FIG. 9AD with a narrow link channel formed between the two wells using a suitable technique such as optical proximity correction channel, and with gate 556 and contacts 558 placed thereover to generate two qdots 552, 554.

Note that the narrow channel link of the induced depletion region separating the two wider quantum wells can have any given orientation, e.g., horizontal, vertical, or any arbitrary angle. In addition, the control gate may overlap the narrow channel link, or it may also overlap the edges of the adjacent wider quantum wells. The former is preferred since it results in a smaller parasitic capacitance and thus a larger Coulomb blockade voltage.

A diagram illustrating a fifth example quantum structure with corner abutting rectangular shaped wells is shown in FIG. 9AF. The structure, generally referenced 560, comprises an aperture tunneling well with an angled drawn link between the two wells and gate overlap only on the link channel 569, and with gate 566 and gate contacts 568 placed thereover to generate two qdots 562, 564.

A diagram illustrating a sixth example quantum structure with corner abutting rectangular shaped wells is shown in FIG. 9AG. The structure, generally referenced 570, comprises an aperture tunneling well with an angled drawn link between the two wells and gate overlap on both the link channel 579 and the wells themselves, and with gate 576 and contacts 578 placed thereover to generate two qdots 572, 574.

It is appreciated that the fabrication of the quantum structure examples described supra is not limited to one process only but can be fabricated using any number of semiconductor processes. Examples include (1) planar semiconductor processes with depletion tunneling, (2) planar semiconductor processes with oxide tunneling, (3) 3D (FinFET) semiconductor processes with depletion tunneling, and (4) 3D (FinFET) semiconductor processes with oxide tunneling.

Single Particle Operation

It is important to note that to achieve quantum operation: (1) carriers (electrons or holes) need to be isolated, (2) information needs to be conveyed to the electrons in either their position or spin (or both), and (3) multiple carriers are allowed to interact (i.e. entangle) before a reading (referred to as detection) of the quantum state is performed.

First, single carriers are separated out of the collectivities of carriers that usually exist in semiconductor layers in classic circuits. A semiconductor layer is formed of a network of semiconductor atoms that contribute carriers to a collective of carriers described by an energy band. Dopants are introduced into semiconductor layers in order to enhance the concentration of a given type of carriers. Donor dopants increase the number of electrons yielding an N-type semiconductor layer while acceptor dopants increase the number of holes yielding a P-type semiconductor layer.

When the semiconductor contains a very large number of carriers acting as a collectivity, adding one carrier to the collectivity or subtracting one carrier from the collectivity does not change the potential. To achieve a single carrier (e.g., single electron) behavior it is best that the considered particle does not have a large collectivity of carriers that it can interact with.

An undoped semiconductor or undoped semiconductor layer has a very low concentration of carriers. It still contains a large number of carriers compared with the single carrier that is needed for quantum operations. Doped semiconductor layers have even more carriers and thus are less attractive for single electron operation.

To achieve single carrier behavior in semiconductor layers it is preferable to first deplete them of carriers before performing the single electron operations. It is relatively easy to deplete an intrinsic (i.e. undoped) semiconductor and even a low doped semiconductor. Depleting a higher doped semiconductor layer is harder and requires much larger potentials to achieve depletion. Furthermore, it is easier to deplete a thin layer of semiconductor than it is to deplete a thick layer of semiconductor. Thus, for building semiconductor quantum structures based on single electron behavior, an SOI process having a thin top active layer and an oxide layer to isolate the top layer from the substrate is preferred.

In such processes, the body of the devices is relatively easy to fully deplete. In most cases even the work function between the gate and the thin active layer is enough to generate a full depletion of the thin layer. In other cases a certain gate voltage may be needed to fully deplete the body of the device. In fully depleted processes, the thin semiconductor layer is depleted of free carriers due to the presence of one or more control gates on top.

Once the semiconductor layer is fully depleted, there are no other free carriers that can interact with the quantum particle(s) and quantum effects can come forth. In a fully depleted well (which may have initially been undoped or low doped), the potential on the control gates on top determines the its profile. Such potential profile may, for example, have valleys and peaks. The valleys is where a carrier may be likely located and the peaks constitute tunneling barriers that may prevent the particle(s) from moving from one position to another.

In such a fully depleted semiconductor layer (CAD drawn layer may be undoped or low doped) a single carrier (e.g., electron) may be injected using an interface device. The particle may be trapped in a given location in the depleted well where the potential has a valley bounded on both ends by tunnel barriers. By appropriately changing the control signals on the gate, the potential in the well and the heights of the barriers can be modified and thus the single particle may move from one location to another in the fully depleted well. This is the basis of the operation of the charge/position quantum qubit.

Classic FET transistors, on the other hand, have higher doped regions for the source and drain. In bulk processes, the higher doped source and drain regions are formed directly in the body well by implanting or diffusing dopants. In fully depleted SOI processes where a thin semiconductor film is deposited on top of the BOX oxide that provides isolation from the substrate, the source and drain regions are realized by depositing another layer of high doped semiconductor on top of the undoped thin layer.

The interface devices have on one side of the gate a higher doped layer that behaves classically and carriers that behave collectively, while under the gate and on the opposite side thereof is the original undoped layer which is fully depleted. The gate terminal determines the height of the tunnel barrier and may allow a single particle to be injected in the fully depleted well. The particle will be localized in the fully depleted well in a region where a valley of the potential is present. From this point on a quantum operation may be performed on the single carrier that was separated from the classic collectivity of carriers present on the classic well of the device.

Half Classic/Half Quantum Interface Device and Example Structures

The interface device disclosed herein is operative to provide a link between classic electronic circuits and quantum circuits. A well is a fairly isolated semiconductor layer that can be part of a device. A classic well is contacted with metal layers to other devices and usually has a large number of free carriers that behave in a collective way, sometimes denoted as a “sea of electrons.” A quantum well, however, is not connected to classic devices that may have a sea of electrons. The quantum well may or may not have contacts and metal on top, but such metal is left floating. A quantum well holds one free carrier at a time or at most a few carriers that have single carrier behavior.

The ability to inject one single carrier at a time is needed to operate a quantum structure. The charge of a carrier (i.e. electron or hole) is 1.6×10⁻¹⁹ Coulomb. The charge is the integral of the current over a given time interval. Classic devices operate with current that are usually in the 0.1 uA and higher level. If a 0.1 uA current is used to inject a single electron, the pulse width of the current needs to be 1.6×10⁻¹² sec. A pulse in the 1 ps range could require clock frequencies in the THz range if implemented straightforwardly with clocks, which are not available in current integrated semiconductor processes. Furthermore, the dependence of the transistor current on the applied voltage is relatively moderate, e.g., quadratic or even linear. Thus, in order to stop the current flow a large voltage difference is required. Such a voltage is much larger than what a typical Coulomb blockade voltage is in currently available semiconductor processes.

To stop the flow of current with a Coulomb blockade voltage, the current dependence on the voltage needs to be very steep, e.g., exponential. Such current to voltage dependencies are achieved in deep subthreshold regimes when a tunneling current is present in the device.

To inject a single electron with a pulse in the 100 ps range requires a current of 1 nA. Such a current puts the small nanometer devices in deep subthreshold mode of operation. In this regime a tunnel current with exponential voltage dependence is established between the two wells/sides of the device.

In classic electronic circuits operating at room temperature if the interface device generates a 1 nA current multiple carriers (i.e. electrons) will be transferred to the second well provided that a closed path is established for the device current. If the second well is connected electrically, there is no force that will oppose the flow of additional carriers in the second well. When the second well is left floating, a different behavior is ensured.

To achieve quantum operation the devices are cooled down to deep cryogenic temperatures such that the thermal noise or thermal agitation of the carriers is minimal. Also, the quantum devices need to use dimensions in the nanometer range, such that the capacitance of the structure is in the 100 aF range. In such cases the Coulomb blockade voltage becomes multi-millivolt level. This is needed since the transport of a single carrier from the classic well to the quantum well requires a change of potential (Coulomb blockade) large enough that the tunnel current is reduced significantly and no further carrier will tunnel to the quantum well. The dependence of the tunnel current on the potential difference between the gate and the well is exponential. Therefore, voltage changes of a few to tens of millivolts can readily stop the further tunneling of subsequent particles.

In a half-classic, half-quantum interface device the Coulomb blockade generated by the tunneling of a single carrier to the quantum well prevents other carriers from tunneling. In order to establish the initial tunneling current from the classic well to the quantum well, a potential difference is established between the well and the control gate. In one embodiment, the interface device is realized by placing a control gate over a continuous well. The potential of the gate which is directly driven or has its potential imposed for example by a capacitor divider such that a depletion region is established under the control gate thereby separating the well into two sections: one classic and one quantum. The classic well is connected to other classic devices using metal layers. In order to control the device with the gate signal, the potential of the classic well needs to be set at a certain reference value. This is done with a classic FET transistor that resets the potential of the classic well during a rest time period.

With the classic well sitting at a V_(classic_ref) potential, the potential of the gate is changed by a control signal such that a subthreshold tunnel current is generated in the interface device. The sign of the gate potential depends on the doping type, the level of the well, and the material of the gate and oxide which in turn set the work function difference. In the case of a P-type well the gate voltage needs to be more positive than the classic well potential, assuming a zero work function difference.

In this manner a pulse signal applied at the gate of the interface device determines the tunneling of precisely one particle (e.g., electron) from the classic to the quantum well. The pulse duration does not need to be very precise. It just needs to be longer than what is needed to securely tunnel a single particle. No further particle will be tunneled, even though the pulse may be longer because of the Coulomb blockade voltage that will exponentially reduce the tunnel current level.

Once a single carrier (e.g., electron or hole) is injected into the quantum well, a pure quantum operation can be performed. Using additional control gates on top of the continuous well which further isolates quantum dots in the structure, the carrier may be transported in a discrete fashion from one qdot to another. If appropriate control signal pulse widths are applied, the particle (actually, its wavefunction) may be split between two or more qdots. In one embodiment, a quantum structure can have a plurality of wells with a plurality of qdots. If the wells are brought in close proximity at least in a certain location, interaction (i.e. entanglement) between quantum particles can occur.

In one embodiment, a quantum structure comprises one or more half-classic, half-quantum interface devices. Each interface device injects a single carrier or multiple carriers but at different time instants, with one carrier at a given time.

The gate-to-classic well potential difference needed to realize the tunneling of the single carrier varies with process and location of the device. It also varies with the temperature of the structure. To mitigate such variability, the gate control signal has adjustability built-in such as via a digital to analog converter (DAC) and a calibration engine to set the appropriate voltage level for each individual injection device (i.e. half-classic, half-quantum interface device).

A diagram illustrating a first example interface device of the present invention in more detail is shown in FIG. 10A. The device, generally referenced 802, comprises a conventionally doped diffusion region 812 and one or more metal contacts 814, gate 806 and gate contacts 804, and a non-doped (intrinsic or no diffusion) or very low doped (n−−, p−−) region 820 having no or low n- or p-doping, diffusion, and no contacts nor metal. The doped diffusion region 812 is either low doped (n−, p−), medium doped (n, p), high doped (n+, p+), or highly doped (n++, p++). The doped semiconductor side 812 of the gate 806 connects to classical semiconductor electronic circuitry 816, which can comprise a particle (e.g., electron) injector controller, a gate imposer controller, and a particle detector in addition to various other control, detection and processing functionalities (see FIG. 2). The gate 806 can also connect to the circuitry 816 (not shown). The non-doped side 820 of the gate 806 connects to quantum semiconductor circuits 818. Thus, half the device contains classic carriers in energy bands and the other half contains quantum carriers in discrete energy levels. The transport of carriers from the classic side to the quantum side of the device is realized through tunneling through highlighted region 808. An appropriate potential applied to the gate is operative to connect a particle from the quantum side to the classic side of the interface device. This way, the quantum particle can electrically join the potential sea of carriers. Note that the labels ‘quantum side’ and ‘classic side’ are for convenience sake since at the fundamental level there is nothing inherently quantum or classic with the two sides of the gate.

In operation, the interface device 802 functions to provide an interface from conventional electronic circuitry located on (or off) the integrated circuit to quantum circuits and vice versa. In particular, the interface device is operative to separate a single quantum particle 824, e.g., electron, etc., from a plurality of particles 822. A single quantum particle is allowed to tunnel (indicated by arrow 810) through the depletion region 808 in an injector mode of operation. An appropriate gate control signal is applied to the gate 806 to establish the energy barrier and to control the tunneling through the depletion region. Note that an appropriate potential might need to be set on doped region 812 prior to this operation. Thus, the interface device functions as an injector tunneling device that allows the tunneling of a single quantum particle, or alternatively a controllable number of particles. When the gate potential is carefully lowered, a single quantum particle (e.g., electron) is allowed to tunnel from the left to the right side of the device.

In addition, in one embodiment, the logical flow of electrons can be provisioned to function in the opposite direction whereby the interface device is part of a circuit that senses and detects the presence of a single particle. In this case, the interface device can serve as the sensor which is coupled to additional classical circuitry (not shown) to detect the presence of single particles. In particular, if the capacitance on the classic side of the device is sufficiently low enough, the presence of a single particle (e.g., electron) on the quantum side of the device can be sensed or detected on the classical side of the device using conventional electronic circuitry, such as 816. This is achieved by detecting the rise in voltage magnitude on the classical side caused by the presence of the single particle on the quantum side upon lowering the barrier of the gate 806. Thus, the interface device is capable of operating bidirectionally as both an injector of a single particle and a detector of a single particle.

Note that in operation, on the classic side of the interface device, the quantum particles, e.g., electrons, are in energy bands, i.e. conduction band and valence band, which enables current flow in classic semiconductor devices. On quantum side of the interface device, the quantum particle is in discrete energy levels with one or two electrons (spin up and down) in each level.

A diagram illustrating a second example interface device of the present invention is shown in FIG. 10B. It is appreciated that the interface device can have many shapes depending on the particular implementation of the invention. In this example, the interface device, generally referenced 830, has an ‘L’ shape and comprises a conventionally low, medium, high, or highly doped region 838 with one or more metal contacts 836, gate 834 and gate contacts 832, and a smaller non-doped (intrinsic) or very low doped region 839 without n+ or p+ doping, contacts, or metal. Note that the ‘L’ shape helps provide shifting on the y-axis and thus increases the distance from other structures.

A diagram illustrating a third example interface device of the present invention is shown in FIG. 10C. In this example, the interface device, generally referenced 840, has a diagonal shape and comprises a conventionally low, medium, high, or highly doped region 848 with one or more metal contacts 846, gate 844 and gate contacts 842, and a smaller non-doped (intrinsic) or very low doped region 849 with n−− or p−− doping.

A diagram illustrating a cross section of a first example semiconductor quantum structure and conventional FET is shown in FIG. 11. The structure, generally referenced 850, comprises a conventional classic FET on the left, a fully quantum device on the right, and a half classic/half quantum interface device in the middle. All three devices are fabricated on substrate 852 and oxide layer 854. It is appreciated that other types of substrates are possible as well.

The classic FET on the left comprises source, drain, and gate including p or n doped well 878, 861 connected to contact 858 and metal 856 structures located on either side of metal or polysilicon (or metal) gate 860 built over oxide layers 851, 853. In classic FET operation, mobile carriers travel from source to drain through inversion channel 855 in accordance with the potential applied to the gate, source and drain terminals. Note that the inversion channel may be pinched wherein carriers are swept by the electric field through the pinched area.

The fully quantum device on the right comprises two qdots in well 879 separated by metal or polysilicon gate 864 and oxide layers 870, 872 over depletion region 868. The gate modulates tunneling (arrow 869) between the two qdots as described in detail supra. Note that the two qdots on either side of gate 864 have no diffusion, contacts or metal.

The half classic/half quantum interface device in the middle comprises metal or polysilicon gate 862 and oxide layers 870, 872 over depletion region 866. The gate modulates tunneling (arrow 867) to allow a single quantum particle to tunnel between doped region 878, 874 on the left side of the gate 862 and the qdot on the right side of the gate. The half classic/half quantum interface structure thus functions to provide an interface mechanism between classic electronic circuitry on the left and quantum circuitry on the right.

A diagram illustrating a cross section of a second example semiconductor quantum structure and conventional FET is shown in FIG. 12. The structure, generally referenced 880, comprises a conventional (i.e. classic) 1-ET on the left, a fully quantum device on the right, and a half classic/half quantum interface device in the middle. All three devices are fabricated on substrate 892 and oxide layer 894.

The classic FET on the left comprises source, drain, and gate including doped well 882, 918 connected to contact 916 and metal 896 structures located on either side of metal or polysilicon gate 898 built over oxide layers 910, 912. In classic FET operation, mobile carriers travel from source to drain through inversion channel 914 in accordance with the potential applied to the gate, source and drain terminals.

The fully quantum device on the right comprises two qdots in well 908 separated by metal or polysilicon gate 900 and oxide layers 902, 904 over depletion region 887. The gate modulates the tunneling (arrow 886) between the two qdots as described in detail supra. Note that the two qdots on either side of gate 900 have no diffusion, contacts or metal.

The half classic/half quantum interface device in the middle comprises metal or polysilicon gate 899 and oxide layers 902, 904 over depletion region 885. The gate modulates the tunneling (arrow 884) between the region on the left of the gate to the region on the right. In this embodiment of the interface device, the doped region 918, 906 of drain of the classic FET is moved closer to the gate 898 and a non-diffusion region is inserted on the left side of the gate 899 in order to reduce parasitic capacitance. The half classic/half quantum interface device functions to provide an interface mechanism between classic electronic circuitry on the left and quantum circuitry on the right.

A diagram illustrating a cross section of a third example semiconductor quantum structure and conventional FET is shown in FIG. 13. The structure, generally referenced 920, comprises a conventional (i.e. classic) FET on the left, a fully quantum device on the right, and a half classic/half quantum interface device (i.e. interface device) in the middle. All three devices are fabricated on substrate 922 and oxide layer 924.

The classic FET on the left comprises source, drain, and gate including doped well 938, 936, 954 connected to contact 928 and metal 926 structures located on either side of metal or polysilicon gate 930 built over oxide layers 942, 944. In classic FET operation, mobile carriers travel from source to drain through inversion channel 940 in accordance with the potential applied to the gate, source and drain terminals.

The fully quantum device on the right comprises two qdots in well 956 separated by metal or polysilicon gate 934 and oxide layers 946, 948 over depletion region 962. The gate modulates tunneling (arrow 964) between the two qdots as described in detail supra. Note that the two qdots 950, 952 on either side of gate 934 have diffusion but no contacts or metal.

The half classic/half quantum interface device in the middle comprises metal or polysilicon gate 932 and oxide layers 946, 948 over depletion region 960. The gate modulates tunneling (arrow 958) between the diffusion region 936, 954 on the left side of the gate 932 and well 956 with diffusion 958 on the right side of the gate. The half classic/half quantum interface device functions to provide an interface mechanism between classic electronic circuitry on the left and quantum circuitry on the right. Note that in one embodiment, similar structures can be built using bulk processes with no oxide layer under the quantum structure but with a depletion region instead.

As described supra, the quantum processor of the present invention comprises a mix of structures including quantum structures, conventional/classic FET structures, and interface devices comprising half classic and half quantum operation which are used to move information from the conventional FET (i.e. non-quantum) domain to the full quantum domain.

A diagram illustrating an example quantum structure with interface devices is shown in FIG. 14. The example structure, generally referenced 670, comprises a middle full quantum structure (dashed circle 683) having gate 689 sandwiched by a left side interface device structure (dashed circle 681) with gate 674 and a right side interface device structure (dashed circle 685) with gate 676. The interface devices 681, 685 comprise a conventional FET (darkened areas 684, 687) on one side of their gate and quantum device on the other side.

The structure 670 comprises two qdots and utilizes well-to-well tunneling through local depleted region. An interface device is located at each end for interfacing with conventional electronic circuits. The potential on the control gate can be applied either with a direct voltage drive network or via a floating impedance division. The well is realized with two rectangular wells having an overlap to create the narrow tunneling channel 671.

A diagram illustrating a first example multiple qdot quantum structure with interface devices on either end thereof is shown in FIG. 15A. The higher complexity semiconductor quantum structure, generally referenced 690, comprises a continuous well with a plurality of imposing control gates 696 and gate contacts 692 that separate it into a plurality of qdots 698. In this example, the well comprises a plurality of overlapping squares connected at their corners to create a narrow tunnel path 699. Located at either ends of the well are interface devices 694 that allow the connection of the reset, injection and detection circuits. The imposer gates 696 receive pulsed control signals that determine the specified quantum operation.

A diagram illustrating a CAD layout of an example quantum structure is shown in FIG. 15B. The layout, generally referenced 700, comprises a continuous well with a plurality of control gates 706 and gate contacts 704 that form a plurality of qdots 702. In this example, the well comprises a plurality of abutting squares connected at their edges to create a tunnel path. Located at either ends of the well are interface devices 708 with contacts 709 that allow the connection of the reset, injection and detection circuits (not shown). Note that these three circuits can be all electrically connected to the same node, for example, 812 in FIG. 10A.

A diagram illustrating a cross section of the quantum structure of FIG. 15A is shown in FIG. 16. The quantum structure has multiple qdots with interface devices at both ends of the well. The single continuously drawn well is separated into a plurality of qdots by the local depletion regions induced by a plurality of control gates. The cross section 710 comprises a substrate 712 and oxide layer 714 on which are fabricated seven qdots 722 comprising six control gates 722 each including oxide layers 728, 730, and polysilicon or metal layer 726, two interface devices 720 each including n or p doped regions 718, 716, contact 711, and metal layer 713, and gate 732.

To illustrate the operation of the quantum structure of the present invention, a series of diagrams are presented that show the steps involved in an example quantum operation starting with a single quantum particle where the local depletion region is under control of the gate.

A diagram illustrating the aperture tunnel barrier for a two quantum dot structure is shown in FIG. 17A. The local depletion region under the control gate divides the structure into two qdots, namely a left qdot storage 741 and a right qdot storage 743. The tunnel barrier imposed by the local depletion region is represented by trace 740. In this phase, the depletion region is wide and the tunnel barrier is high (referenced 742) and the particle 746 cannot tunnel to the right qdot storage and is trapped in the left qdot storage.

A diagram illustrating a first example change in the aperture tunnel barrier for the two quantum dot structure is shown in FIG. 17B. The tunnel barrier imposed by the local depletion region is represented by trace 744. In this phase, an appropriate potential is applied to the control gate to cause the depletion region to narrow thus lowering the tunnel barrier (referenced 745). This permits the particle 748 to travel to the right qdot storage and the particle is in the left and right qdots at the same time.

A diagram illustrating a second example change in the aperture tunnel barrier for the two quantum dot structure is shown in FIG. 17C. The tunnel barrier imposed by the local depletion region is represented by trace 750. In this phase, the potential applied to the control gate is adjusted to cause the depletion region to widen again thus raising the tunnel barrier (referenced 752). This effectively traps the two split particles 747, 748 (i.e. the wavefunction of the particle is split) and prevents them from traveling from one qdot to the other through the tunnel barrier. In quantum fashion, the charge carrier is split between the two qdots. When performing detection, however, the carrier will only be on one side with a corresponding probability.

Thus far only electric control of semiconductor quantum structures has been presented wherein the spin of the quantum particle is ignored. An alternative manner of controlling the semiconductor quantum structure is to control/select the spin of the quantum particle using a magnetic field from an inductor/coil or a resonator. A property of particles is that they tend to align their spins to any external relatively strong magnetic field. A diagram illustrating an example quantum structure surrounded by a spin control magnetic coil is shown in FIG. 18.

The structure, generally referenced 760, comprises a resonator 763 or one or more turns of a coil 762 surrounding a continuous well divided into two qdots 764 by control gate 766 and connected by tunnel path 768. Along with the electrical control of the imposing gate, this structure also uses the magnetic field generated either by (1) an inductor 762 or (2) a resonator 763 that surrounds the entire quantum structure to select the spin of the particle. Note that both are shown in the figure but in practice typically only one is implemented. Note also that both static and ac magnetic fields can be generated and used. In addition, the inductor may overlap only a local area including one or several quantum structures or it can overlap the global area where the quantum core is implemented. In this manner, local magnetic control or global magnetic control can be implemented.

As described supra, the quantum computer operating environment employs cooling at cryogenic temperatures. In addition, electric and magnetic field shielding is provided. The cryostats used typically comprise relatively large metal structures that act as good shields. In one embodiment, the metal cavity of the cryostat creates a high quality resonator that generates a magnetic field to control the semiconductor quantum structures at its interior.

A diagram illustrating a second example multiple qdot quantum structure is shown in FIG. 19. The structure, generally referenced, 770, comprises a blended continuous well path 772 overlapped by a plurality of control gates 776 with contacts 774 (three in this example). Here the width of the vertical segments of the control gates and the vertical and horizontal segments of the well are the same, i.e. a “boomerang” structure in which the width of the wider well regions is made equal to the width of the narrow channel links. Such a structure results in a more compact realization of the quantum structure. Note that the regions between control gates form the quantum dots, while the regions under the control gates realize the induced depletion regions through which tunneling occurs. It is appreciated that any number of qdot structures can be realized depending on the number of control gates implemented. Note that in one embodiment, such structures can be implemented using either planar or 3D semiconductor processes.

A diagram illustrating a third example multiple qdot quantum structure is shown in FIG. 20. In an alternative embodiment, the semiconductor structure comprises a bended well path overlapped by gates using horizontal and inclined well segments. Note that vertical segments also possible. In particular, the structure, generally referenced, 780, comprises a blended continuous well path 782 overlapped by a plurality of control gates 786 with contacts 784 (three in this example) using horizontal and inclined well segments. Here too the width of the vertical segments of the control gates and the vertical and horizontal segments of the well are the same, i.e. a “boomerang” structure in which the width of the wider well regions is made equal to the width of the narrow channel links. Such a structure results in a more compact realization of the quantum structure. Note that the regions between control gates form the quantum dots, while the regions under the control gates realize the induced depletion regions through which tunneling occurs. It is appreciated that any number of qdot structures can be realized depending on the number of control gates implemented.

A diagram illustrating a fourth example multiple qdot quantum structure is shown in FIG. 21. In an alternative embodiment, the semiconductor structure comprises a bended well path overlapped by gates using horizontal and rounded well segments. Note that vertical segments also possible. In particular, the structure, generally referenced, 790, comprises a blended continuous well path 792 overlapped by a plurality of control gates 796 with contacts 794 (three in this example) using horizontal and rounded well segments. Note that the regions between control gates form the quantum dots, while the regions under the control gates realize the induced depletion regions through which tunneling occurs. It is appreciated that any number of qdot structures can be realized depending on the number of control gates implemented.

Quantum State Detection

In semiconductor quantum structures and circuits, the qubits (i.e. elementary quantum information units) are encoded by the state of particles or carriers inside one or more semiconductor layers. To help to achieve the single carrier behavior, the semiconductor layers are usually fully depleted. In the case of spin qubits the detection includes determining the spin orientation of a given carrier (e.g., electron or hole), while in the case of charge qubits (i.e. position qubits) the detection includes determining if the carrier is present or not in a given qdot.

Classically, a bit can have only two values “0” and “1”. In the quantum domain, however, a qubit can have a large number of values given by any constrained combination of the two base quantum states |0> and |1>. This is provided by the superposition character of the quantum states.

When a quantum state is detected, the quantum state is collapsed into a base state which corresponds to a classic state with a given probability associated with it. For example, in the detection of a charge qubit, the outcome can be either: (1) the carrier is present in the detection qdot which corresponds to the base state |1>; or (2) the carrier is not present in the detection qdot which corresponds to the base state |0>. To determine the value of a quantum state, a number of successive quantum experiments are performed to get the average presence probability of the detected carrier. By computing the number of |0>s and |1>s that are obtained in the detection, the probability of the quantum state is determined.

For example, consider the Hadamard equal distribution quantum state denoted by 0.707|0>+0.707|1> where the carrier is split equally into two qdots of the quantum gate. From the quantum perspective, this means the carrier is present simultaneously in both qdots. In the classic view, the electron cannot be split and it either is present in a given qdot or it is absent from that qdot. When detecting a Hadamard state multiple times it is expected to obtain an equal number of collapses to the |0> base state (i.e. the carrier is absent) and to the |1> base state (i.e. the carrier is present) in the detected qdot. If the quantum state has a given rotation and it has a larger |1> base state component (a|0>+b|1> with b>a) then at detection more collapses to the base state |1> should occur. If in contrast, the quantum state has a rotation towards the |0> base state (a|0>+b|1> with a>b) then more collapses to the base state |0> should occur.

In order to perform detection of a quantum state contained in a quantum device, the quantum structure is connected to classic devices. This is achieved using an interface device, described in detail supra. Such interface devices are half-quantum and half-classic in their nature or interpretation. In one embodiment, the detector circuit itself comprises classic devices that process charge, current, and voltage. The quantum devices operate with single carrier (e.g., electron or hole), or a small controllable number thereof, while the interface device extracts a single carrier from a sea of collective electrons in the classic world or vice versa injects a single carrier into a classic world sea of collective carriers.

In one embodiment, the classic device of the detector is connected at a quantum structure using a floating well, in which the interface device has a quantum well on one side and a floating classic well on the other. Since the classic well is set to be floating, the injection of a single carrier may result in a noticeable well potential change that can be amplified further.

In another embodiment, the classic device of the detector is connected at a quantum structure using floating gate detection. In this case, the interface device is realized by a device having a plurality of gates, one of them being shared with a classic FET detector device. When the carrier arrives under the floating gate of the interface device it changes the potential of the gate, which in turn can be measured by the classic FET of the detector which shares the gate with the interface device.

Floating Well Detection

In floating well detection, the quantum particle is injected from the quantum device (if it happens to be present there) into a classic floating well that is in turn connected to the input of the classic detector circuit. An equivalent schematic of the quantum circuit, generally referenced 990, together with its associated interface and classic circuits is shown in FIG. 22A. A top plan layout view of the circuit is shown in FIG. 22B and a cross section of the circuit is shown in FIG. 22C. The quantum circuit 990 comprises several layers including substrate 1010, BOX oxide 1008, and undoped fully depleted layer 1006. Doped regions 1020 are fabricated over the fully depleted layer.

In one embodiment, before starting a quantum operation, the entire quantum structure is reset, i.e. the entire quantum well is flushed of any free carriers. Since the quantum well is fully depleted, there are no carriers in it. A reset operation is performed by one or more classic Mreset devices 992 by appropriately controlling the interface quantum gates (Qinterface) 994 and imposer quantum gates (Qimp) 996. The classic Mreset device comprises metal contacts 1002 on its terminals realized by doped semiconductor layers 1020. Considering the SOI semiconductor process as an example, the source and drain doped diffusions are fabricated above the undoped fully depleted device body 1006. The Mreset device establishes a reference potential for the classic side of the classic to quantum interface device on the left. During the quantum operation it is assumed that this potential does not change much due to leakage currents.

In one embodiment, quantum operation begins by initially resetting the classic well to a reference potential then setting it floating during the detection time interval. A single carrier (e.g., electron or hole, if one happens to be present there) is injected from a classic well 1022 where a sea of carriers have a collective behavior, into a quantum well 1024 where single carrier behavior can occur. An appropriate potential is applied to the gate 1004 of the Qinterface device 994 to control the tunneling of a single particle 1012 to the quantum side by lowering the tunneling barrier. Once the single particle is injected into the fully depleted well 1024, it moves according to the potential distribution change determined by the plurality of quantum imposing gates (Qimp) 996. In one embodiment, the Qimp gates determine the creation of valleys in the potential distribution that is progressively shifted from left to right and thus determine the movement of the particle 1012. Depending on the timing and pulse widths of the Qimp signals, a carrier may be split between different locations in the fully depleted well in which two or more potential valleys may be realized. This is the base of generating the superposition quantum states (a|0>+b|1>).

At the opposite end of the well, a second interface device 998 provides the interface in the other direction from the quantum well 1026 to the classic well 1014. In one embodiment, the classic well is left floating (no dc path to ground) such that the potential injection or transfer (by virtue of the connecting transistor 998) of a single carrier can generate a measurable change in potential that is further processed by the detector classic circuit 1000. Since the particle is injected (or transferred) from the quantum well into a classic well, the quantum state collapses. This detection is destructive since the quantum state is destroyed during the measurement process. It is destroyed specifically during the instance the particle sees a low resistance path, i.e. is connected, to the sea of carriers on the classic side. It is noted that such destructive detection can be performed only once per quantum operation. Furthermore, it is noted that another reset device similar to 992 can be connected to the same node 1014 as that connected to the detector 1000. Likewise another detector similar to 1000 can be connected to the reset device 992 (node 1003). These two types of circuits operate in a time shared manner in which the active time slots allocated to them can be different. Their high resistance during the inactive time slots ensures no conflicts.

The floating classic well 1014 is connected to the gate 1016 of a detection device 1000. The floating well and the gate 1016 of the detector Mdetector have a certain total capacitance. The voltage change in the signal at the gate 1016 of Mdetector is given by ΔV=e/C where e is the carrier charge 1.6×10⁻¹⁹ Coulomb and C is the total capacitance of the floating well (1014 and possible 1026) and gate. In one embodiment, the charge to voltage conversion is followed by classic voltage or transconductance amplifiers depending on the voltage mode or current mode operation of the classic detector circuit 1000. Note that the entire single carrier (e.g., electron) injection, quantum processing/imposing and detection is short in comparison with the decoherence time of the particle in the given semiconductor structure.

Note that other classic analog, mixed signal or digital circuits are preferably kept an exclusion distance away from the quantum structure 990 in order to avoid undesired parasitic interaction with the quantum particle(s) that could lead to quantum decoherence.

Floating Gate Detection

The second option for the detection of the quantum state is to use a floating gate. In this case the classic device of the detector Mdetector is connected to the same floating gate that goes over the quantum well. An equivalent schematic of the quantum circuit, generally referenced 1030, together with its associated interface and classic circuits is shown in FIG. 23A. A top plan layout view of the circuit is shown in FIG. 23B and a cross section of the circuit is shown in FIG. 23C. The quantum circuit 1030 comprises several layers including substrate 1050, BOX oxide 1048, and undoped fully depleted layer 1046. Doped regions 1058 are fabricated over the fully depleted layer.

Similar to the floating well detection circuit 990 described supra, the quantum procedure starts with the reset of the structure 1030 using one or more classic Mreset devices 1032 along with appropriate control of the interface quantum gates (Qinterface) 1034 and imposer quantum gates (Qimp) 1036 such that all free carriers in the quantum structure are flushed out. The classic to quantum Qinterface device 1034, operative to inject a single carrier 1052 into the quantum structure, has a half-classic and half-quantum operation. It comprises a doped and metal contacted classic well 1054 on the left side of its gate 1044 and a floating quantum well 1056 on the other side. In one embodiment, the connection between the Mreset and Qinterface devices on the classic side is realized with contacts and metal layers 1055. Note that the Mreset and Qinterface devices may share the same active layer or may be done in separate active layers.

The quantum imposer (Qimp) devices 1036 determine the specific quantum computation performed. There is at least one Qimp quantum control gate. Alternatively, the circuit may comprise any number of Qimp devices as large as feasible in the actual implementation using a given semiconductor process.

The last three gates over the quantum well on the right side of the circuit 1030 form a quantum to classic Qinterface device 1038, 1064, 1062. Note that alternatively, the Qinterface device may be located in the middle of a quantum well. One of the three gates (1060) is the floating gate which connects to the Mdetector classic detector device 1040. In one embodiment, the carrier is moved under the floating gate by controlling the potential distribution with the two adjacent gates 1059, 1061. The presence of the quantum carrier under the floating gate causes a change of the potential of the quantum gate which is sensed by the Mdetector detector device 1040 and amplified further.

After the first measurement is performed, the quantum carrier can be moved away from under the floating gate 1060 of the interface device. The floating gate initial potential is set during the reset time to a level that allows the proper operation of the Mdetector classic detector device. Such potential may be reset for example with a second classic Mreset device (not shown) connected to the gate of the Mdetector device.

An example potential diagram for the floating gate detection circuit is shown in FIG. 24. The last quantum imposer gate Qimp 1076 together with the three gates 1077, 1078, 1079 of the quantum to classic interface device (Qinterface) 1070 are shown. In this example, two ‘helper’ gates (left gate 1077 and right gate 1079) are controlled and not floating while only the middle gate 1078 is floating and used for actual detection. The middle floating gate 1078 is connected to the detector circuit 1040 (FIG. 23A). It is appreciated that the Qinterface device may comprise more or less than three gates. For example, the detection can be performed using only two interface device gates, i.e. one floating and one controlled.

In operation, the particle is moved one or more times under the floating gate to perform detection (i.e. nondestructive measurement). Multiple measurements are performed under the detection gate for the same quantum experiment. A measurement is made each time the particle moves under the floating gate 1078. Note that the movement is speculative in nature since it is not known a priori whether there is a particle present or not as this is what is being measured. If no particle is detected, then of course no movement actually takes place.

With floating gate detection, a gate overlaps the last region of a quantum well where the presence of a particle is to be detected. Note that the potential of the floating well can be set initially, for example during the reset process, to a reference value appropriate for the detector circuitry. It should, however, be subsequently allowed to be floating such that it can sense the presence or absence of a particle under it, e.g., carrier, electron, hole, etc.

In the floating gate detection process the quantum state or qubit is allowed to move under the floating gate. If a particle is present than the potential of the gate changes from the reference potential it was initially set to, while the particle is not present than the potential of the gate does not change due to the quantum state moving under the gate.

Note that in idealized circuits there are no parasitic leakage currents and the potential of a floating gate can remain for relatively long periods, ideally to infinity or until it is again reset to the potential it achieved at the end of processing. In real circuits, however, parasitic leakage currents typically exist (e.g., a gate over a well may have a certain leakage current from the gate to the well). Such current changes the potential of the floating gate independent of the presence or absence of the quantum particle.

To prevent such floating gate potential change due to leakage, numerous well-known circuit techniques can be applied, including performing the detection quickly such that there is not enough time for the floating gate potential to change significantly due to leakage. In this case a significant potential change is a fraction of the potential change determined by the presence of the quantum particle, e.g., 10% or 20%. Another technique is to use a replica floating gate that never gets a quantum particle but has similar leakage current with the detection floating gate. By measuring the differential signal between the detection floating gate and the replica floating gate, the voltage change due only to the presence or absence of the quantum particle can be detected, while any parasitic voltage change due to leakage current is rejected as a common mode signal.

In one embodiment, the actual operation of the floating gate detection consists in modifying the potential in the proximity of the floating gate such that the quantum particle is moved in a controlled fashion under the floating gate and then away from it.

Since the quantum particle can be moved multiple times under the floating gate and then away from it, this detection is non-destructive and can be performed multiple times. By performing the detection multiple times any parasitic effect due to inherent noise in the system is eliminated or attenuated. Note that the number of consecutive non-destructive detections that can be performed, however, depends on the decoherence time of the quantum state in the given process technology and given physical structure.

With reference to FIG. 24, to impact the potential around the floating gate and thus allow the quantum particle to move under the floating gate and then away, multiple additional helper control gates are used. In one embodiment, a single helper control gate is used located on one side of the main floating detection gate. In another embodiment, two helper control gates are used, one on each side of the main detection floating gate, as shown. Alternatively, additional helper control gates can be placed around the main detection floating gate. The further away the helper gate is placed, however, the less impact it has on the potential profile around the detection floating gate. This is why the most effective are the helper gates directly to the left and right of the main detection gate.

A quantum structure includes a number of control gates, also called imposers that determine the specific quantum operation performed. After the last imposer has performed its function, the desired quantum computation has finished and the quantum state is ready for detection.

In position based semiconductor quantum structures the detection entails determining whether or not the particle is present in the last quantum dot of the structure, past the last imposer. If the quantum state is one of the base states, i.e. particle present or absent, then the detection can be done only once (in the absence of system noise). When noise is present, multiple detections may be desired to reject or attenuate the impact of the system noise.

If the quantum state is a general superposed state, the particle has a certain probability of being present in the last detection quantum dot. To measure the quantum state, the detection is performed multiple times. The percentage of positive (i.e. present) outcomes versus the total number of measurements represents the probability corresponding to the measurement of the corresponding quantum state. Similarly, the percentage of negative (i.e. absent) outcomes may be used.

In trace (A) the control signals on the left and right helper control gates are such that the energy profile is high and the quantum particle is not allowed to move towards the floating detection gate. The particles flow towards the positions with lower energy. If a potential profile is drawn instead, the electrons go to higher potential level locations. The situation is reversed for the holes that go to the regions of higher energy. From the potential perspective, the holes go to the lower potential levels.

Trace (B) illustrates the case when the control signals on the left and right helper control gates are modified such that the energy profile level is lowered (1080) in the area surrounding the floating detection gate. This allows the quantum particle to extend over the entire physical location where the energy profile is low. This also includes the region under the floating detection gate.

Trace (C) shows the control signals of the left and right helper control gates changed such that the region of low energy profile is restricted to a narrow region essentially under the floating detection gate. Now that the quantum particle is localized in a very narrow region under the floating detection gate. This results in a relatively large (i.e. measurable) change in the potential of the floating gate. When the quantum particle is distributed over a wide area, the change in potential is much smaller, making it harder to measure. Having the particle located directly under the floating gate generates a change in potential of the floating gate which can be measured and amplified by the Mdetector circuit 1040 (FIG. 23A) using one or multiple classic FET devices.

The quantum particle is then moved away from the floating detection gate. As shown in trace (D), first the right helper control gate is used to enlarge the area of low energy towards the right side, away from the floating detection gate. In this case the energy profile is still low under the floating detection gate which allows the quantum particle to spread both under the floating gate and away from the floating gate.

In a second step as shown in trace (E), the helper control gates are used to raise the energy profile in close proximity of the floating detection gate, allowing the quantum particle to extend away from the floating detection gate. In this manner, the quantum particle is moved away from the floating gate and the first detection has ended. The quantum state is still intact. It has not been destroyed through the first detection. A second detection may be performed by moving the quantum particle under the floating detection gate again.

Trace (F) shows how the control signals on the two helper control gates are again enlarging the region with low energy profile, allowing the quantum particle to move again under the floating detection gate. The low energy level area remains wide and the quantum particle is spread both under the floating detection gate and away from the floating gate. As such the change in potential of the detection gate is low and harder to measure.

In trace (G) the control signals on the helper control gates again determine the narrowing of the energy valley where the quantum particle is allowed to spread to a relatively narrow region under the main floating detection gate. As such the quantum particle moves a second time under the gate and a second non-destructive quantum detection is performed.

The detection process can continue with multiple subsequent detections. In trace (H) the helper control gates are used to again widen the low energy level where the quantum particle is present. In this way the quantum particle is spread under and away from the floating detection gate.

In trace (I) the helper control gates restrict the area of low energy level where the quantum particle can be present to a region away from the floating detection gate.

In this manner, the process can continue with further subsequent movements of the quantum particle under the floating detection gate and away from the floating detection gate, both on the left side and on the right side.

A key advantage of floating gate detection is that it allows multiple detection of the same quantum state, without the need of repeating the entire quantum computation since the particle's wavefunction does not collapse in the detection process. Therefore, instead of performing the entire quantum experiment multiple times, the quantum experiment is performed once but the results are measured multiple times. This shortens the overall computation time thus increasing the speed of quantum computation, and thus provides accelerated quantum computation.

In the case of the destructive floating well detection, the quantum particle is lost with each detection. Thus, performing multiple floating well detections require multiple executions of the entire quantum operation, which in turn takes a longer time. The more time spent on detection reduces the speed of quantum operation and thus reduces the effective quantum acceleration factor with respect to a classical computation.

In another embodiment, the floating gate detection may be followed by a floating well detection which finally collapses the quantum state. By using both methods of detection, a more sophisticated detection scheme can be built with lower error rate. By looking at the correlation between the two types of detection, built-in detection error correction can be realized.

3D Semiconductor Quantum Structures

The present invention provides a semiconductor quantum structure that uses a 3D semiconductor process with very thin semiconductor fins having much smaller parasitic capacitance to the gate. This results in higher Coulomb blockade voltages and thus quantum circuits that are easier to control with classic electronic circuits with more noise floor margin. Two semiconductor islands are isolated in a continuously drawn fin using an overlapping control gate that induces a local depletion region in the fin. The tunneling between one island in the fin to the other is controlled by the control gate that imposes the potential on the fin. By modulating the potential applied to the control gate, a controlled fin-to-fin tunneling through the local depletion region is achieved, realizing the function of a position/charge qubit. More complex structures with higher number of qdots per continuous fin and larger number of fins can be constructed. 3D semiconductor processes can be used to build such fin-to-fin tunneling quantum structures. Hybrid 3D and planar structures can be built as well. By combining a number of such elementary quantum structures a quantum computing machine is realized.

A diagram illustrating an example 3D semiconductor quantum structure using fin to fin tunneling through local depletion region is shown in FIG. 25. The quantum structure, generally referenced 1840, comprises a continuously drawn fin 1846, overlapping control gate 1843, two isolated semiconductor well and fin structures realize qdots #1 and #2 1842, local depletion region 1848, tunneling path 1841, and particle, e.g., electron or hole, 1844. A diagram illustrating a three dimensional view of an example 3D semiconductor quantum structure with fin to fin tunneling under control of a control gate is shown in FIG. 26. The quantum structure, generally referenced 1850, comprises fins with portions 1851, 1853, overlapping control gate 1854, substrate 1855, and local depletion region 1852. Note that the well may be omitted and the qdot realized by the semiconductor fin area only.

With reference to FIGS. 25 and 26, the control gate layer overlaps the fin on three sides and creates a local depleted region which isolates the two sides when the potential barrier is high. Note that overlapping the fin provides better control over the structure. A thin oxide layer separates the semiconductor fin from the control gate. When the control terminal lowers the potential barrier, tunneling can occur from one side of the fin to the other side. The tunneling is controlled by the control terminal that imposes the potential in the semiconductor fin. If the tunnel barrier is high, the quantum particle is locked in its prior state. When the potential on the control terminal lowers the barrier, the quantum particle can tunnel from one qdot to the other. Depending on the pulse width of the control signal, the quantum particle completely or partially tunnels. In the latter case, the quantum particle (precisely, its wavefunction) is distributed between the two qdots, i.e. spatial entanglement. Note that in real implementations, the quantum structure generally has a deformed complex 3D shape where the depletion region depends on the particular implementation and semiconductor process used. The structures shown herein are for illustration purposes only.

A diagram illustrating a cross section, side view, and top view of an example 3D two qdot quantum structure using local fin depletion tunneling is shown in FIG. 27A. The quantum structure, generally referenced 1860, comprises substrate 1869, optional oxide layer 1861, wells 1862, 1865, fin 1863, gate oxide 1866, and overlapping control gate 1864. Note that the dotted line indicates the optional oxide layer that isolates the 3D quantum structure from the substrate. The substrate may comprise standard resistivity, high resistivity, or isolating substrates.

The tunneling through a local depletion region in the quantum structure is induced in a fin by the overlapping control gate. When the barrier is high, the local depleted region is wide and virtually no tunneling current is allowed. When the barrier is lowered, the local depleted region shrinks in width and a sizeable leakage tunneling current appears, which allows the particle to move from one qdot to the other. If the particle has not completed the move from one qdot to the other, it will spread (equally or non-equally) between the two qdots to achieve spatial particle entanglement.

A diagram illustrating a cross section, side views, and top view of an example 3D multiple qdot quantum structure using local fin depletion tunneling is shown in FIG. 27B. The quantum structure, generally referenced 1870, comprises substrate 1879, optional oxide layer 1871, wells 1872, 1876, fin 1873, gate oxide 1877, and overlapping control gates 1874, 1875. Note that the dotted line indicates the optional oxide layer that isolates the 3D quantum structure from the substrate. The substrate may comprise standard resistivity, high resistivity, or isolating substrates. The quantum structure 1870 is useful when quantum transport is needed, i.e. quantum shift and particle spatial entanglement, and can be realized in bulk 3D semiconductor processes, e.g., FinFET, or in SOI 3D semiconductor processes.

A diagram illustrating two example double V fin-gate-fin structures having two wells placed in close proximity allowing quantum particles to interact is shown in FIG. 28A. The quantum interaction gate, generally referenced 1880, comprises two 3D structures comprising a plurality of qdots 1882, 1888, fins 1884, control gates 1886, and interaction qdots 1881.

In this embodiment, the inner two semiconductor wells 1881 come in very close proximity thereby allowing a strong interaction between particles or distributed particles in the two qdots. The distance between other pairs of qdots is significantly larger and thus the interaction between corresponding particles is much smaller, ideally negligible. In this manner, the double V quantum structure shifts two or more particles into specific positions for a well-controlled interaction and then transports them apart. The preparation of the quantum state also happens when particles are further away and thus can be done largely independent one from the other. This also allows a well-controlled interaction between particles only when they are in specific qdots and when the control signals are configured to enable the interaction.

A diagram illustrating an example 3D semiconductor quantum structure using fin-to-fin tunneling through a local depleted region with a shared well between two fin paths providing bifurcation is shown in FIG. 28B. The quantum structure, generally referenced 1890, comprises a plurality of qdots 1892, namely qdots #1, #2, #3, #4, fins 1896, and control gates 1894. The well of qdot #2 1898 overlaps two fins to provide path bifurcation whereby particles can move between qdots #1 and #4 and between qdots #3 and #4.

Note that this quantum structure can realize either a bifurcation of the quantum operation path or a merger of the quantum operation path. This structure is useful in creating more complex quantum structures. Note also that the control gates overlapping the two fins and separating qdots #1 and #3 can be separated (as shown) or can be shared (not shown).

A diagram illustrating an example quantum structure with dummy gates and gate cuts that separate control and dummy gates is shown in FIG. 28C. The quantum structure, generally referenced 1900, comprises qdots 1902, namely qdots #1 to #6, fins 1904, control gates 1901, contacts 1903, dummy gates 1906 not used in operation of the circuit, and gate cuts 1908. Depending on the actual 3D semiconductor process used, dummy gates may be needed but they remain floating with no potential. The gates need to be equally spaced and on the edges of the well. In addition, they may need to be cut in order to prevent unwanted interactions. The cutting may be done on top of a dummy fin, or alternatively without the fin. Although 12 control gates are shown, only four are active.

A diagram illustrating an example hybrid planar and 3D semiconductor quantum structure using both fin-to-fin and well-to-well tunneling through local depletion region is shown in FIG. 28D. The quantum structure, generally referenced 1910, comprises 3D qdots 1912, fins with portions 1914, 1913, 3D control gate 1918, planar qdots 1911, and planar control gate 1916. This hybrid embodiment uses both 3D and planar tunneling structures which is possible in a 3D semiconductor process. The inner quantum structure is planar with two overlapping wells (i.e. qdots) and uses well-to-well tunneling through a local depletion region. The outer, i.e. left and right, quantum structures are 3D and use fin-to-fin tunneling through a local depletion region. Note that the two types of tunneling have different barrier levels and thus require different control gate signals.

The present invention also provides a semiconductor quantum structure that uses a 3D semiconductor process used to fabricate two semiconductor fins and an overlapping imposing control gate that constitutes the tunneling path from one semiconductor qdot to the other. The tunneling is controlled by the control gate that imposes the potential on the tunneling path. By modulating the potential of the imposer gate, a controlled fin-gate and gate-fin tunneling through the thin oxide under the control gate is enabled, realizing the function of a position/charge qubit. More complex structures with higher number of qdots per continuous well and larger number of wells can be built. Both planar and 3D semiconductor processes can be used to build well/fin-to-gate and gate-to-fin/well tunneling quantum structures. Hybrid 3D and planar structures can be built as well. By combining a number of such elementary quantum structures a quantum computing machine is realized.

A diagram illustrating an example 3D semiconductor quantum structure using fin-to-gate tunneling through oxide is shown in FIG. 29. The quantum structure, generally referenced 1920, comprises two wells 1921, 1927 with fin structures 1923, 1926 to realize the quantum dots #1 and #2, a gate layer with oxide 1924 overlaps both fins and creates a tunneling path from one fin to the other. A diagram illustrating a three dimensional view of an example 3D semiconductor quantum structure using fin-to-gate and gate-to-fin tunneling through oxide is shown in FIG. 30. The quantum structure, generally referenced 1930, comprises fins 1932, 1938, overlapping control gate with oxide layer 1936, substrate 1931, and local depletion region 1934. Note that the well may be omitted and the qdot realized by the semiconductor fin area only.

With reference to FIGS. 29 and 30, the tunneling is controlled by the control terminal that imposes the potential on the tunneling gate. In one embodiment, the control gate is substantially floating but it is electrostatically coupled to the control terminal nearby (not shown). If the tunnel barrier is high, the quantum particle is locked in its prior state. When the control terminal determines a lowering of the barrier, the quantum particle is allowed to tunnel from one qdot to the other. Depending on the pulse width of the control signal, the quantum particle either completely or partially tunnels through. In the latter case, the quantum particle is distributed between two qdots to achieve a spatial superposition state. A thin oxide layer separates the semiconductor fin from the control gate. Note that in real implementations, the quantum structure generally has a deformed complex 3D shape where the depletion region depends on the particular implementation and semiconductor process used. The structures shown herein are for illustration purposes only.

A diagram illustrating a cross section, side view, and top view of an example 3D semiconductor quantum structure using fin-to-gate tunneling through oxide is shown in FIG. 31. The quantum structure, generally referenced 1950, comprises substrate 1951, optional oxide layer 1957, wells 1952, fins 1953, 1955, gate oxide 1956, and overlapping control gate 1954. Note that the dotted line indicates the optional oxide layer that isolates the 3D quantum structure from the substrate, i.e. SOI process. The substrate may comprise standard resistivity, high resistivity, or isolating substrates.

The tunneling through the oxide in the quantum structure is induced in a fin by the overlapping control gate. When the barrier is high, virtually no tunneling current is allowed. When the barrier is lowered, tunneling through the gate oxide allows the particle to move from one qdot to the other. If the particle has not completed the move from one qdot to the other, it will spread (equally or non-equally) between two qdots to achieve a superposition state.

A diagram illustrating a cross section of an example 3D semiconductor quantum structure using fin-to-gate and gate-to-fin tunneling is shown in FIG. 32. The quantum structure, generally referenced 1940, comprises substrate 1941, optional oxide layer 1942, fins 1945, 1946, gate oxide 1944, and overlapping control gate 1943. As described supra, the tunneling through the oxide layer 1944 is controlled by the overlapping control terminal that imposes the potential on the control gate. If the tunnel barrier is high, the quantum particle is locked in its prior state. When the control terminal determines a lowering of the barrier, the quantum particle is allowed to tunnel from one qdot to the other.

A diagram illustrating a top view of an example two qdot 3D semiconductor quantum structure using fin-to-gate tunneling through oxide is shown in FIG. 33. The quantum structure, generally referenced 1990, comprises two wells 1992, 1996 with fin structures 1993 that realize quantum dots #1 and #2 and a control gate layer with oxide 1994 overlapping both fins creating a tunneling path 1995 for particle 1992 from one fin to the other.

Note that different shapes can be used for the layers used to construct the quantum structure, e.g., squares, rectangles, polygons, circles, composed shapes, etc. as described supra. In this embodiment, two wells are added, one to each fin which crosses the well in the middle. When the control terminal lowers the barrier, the quantum particle in the left qdot tunnels to the right qdot.

A diagram illustrating an example double V quantum interaction structure using 3D semiconductor process with fin-to-gate tunneling is shown in FIG. 34A. The quantum interaction gate, generally referenced 1960, comprises two 3D structures comprising a plurality of qdots 1964, fins 1968, control gates 1966, and interaction qdots 1962.

In this embodiment, the inner two semiconductor wells 1962 come in very close proximity thereby allowing a strong interaction between particles or distributed particles in the two qdots. The distance between other pairs of qdots is significantly larger and thus the interaction between corresponding particles is much smaller, ideally negligible. In this manner, the double V quantum structure shifts two or more particles into specific positions for a well-controlled interaction and them transports them apart. The preparation of the quantum state also happens when particles are further away and thus can be done largely independent one from the other. This also allows a well-controlled interaction between particles only when they are in specific qdots and when the control signals are configured to enable the interaction.

A diagram illustrating an example quantum structure with fin-to-gate tunneling with dummy gates and cuts to create dummy fins is shown in FIG. 34B. The quantum structure, generally referenced 1970, comprises a plurality of qdots 1972, fins 1973, control gates 1974, contacts 1975, dummy gates 1971 not used in operation of the circuit, and gate cuts 1976. Depending on the actual 3D semiconductor process used, dummy gates may be needed which remain floating with no potential. The gates need to be equally spaced and on the edges of the well. In addition, they may need to be cut in order to prevent unwanted interactions. The cutting may be done on top of a dummy fin, or alternatively without the fin.

A diagram illustrating an example hybrid planar and 3D semiconductor quantum structure using both fin-to-gate and well-to-gate tunneling is shown in FIG. 34C. The quantum structure, generally referenced 1980, comprises 3D qdots 1982, fins 1984, 1986, 3D control gate 1986, planar qdots 1988, and planar control gate 1989. This hybrid embodiment uses both 3D and planar tunneling structures which is possible in a 3D semiconductor process. The inner quantum structure is planar with two wells (i.e. qdots) and uses well-to-gate tunneling through oxide. The outer, i.e. left and right, quantum structures are 3D and use fin-to-fin tunneling through oxide. Note that the two types of tunneling have different barrier levels and thus require different control gate signals.

A diagram illustrating an example initialization configuration for a quantum interaction structure using tunneling through gate-well oxide layer is shown in FIG. 35. The circuit comprises a classic well 1100, single particle (e.g., electron) injector circuit 1102, quantum well 1104, and control gate 1108. The circuit is operative to separate a quantum behaving electron from the sea of electrons present on the surrounding classic semiconductor structures, such as well 1100. The single electron injection circuit 1102 takes only one electron from the classic well situated on its left side and injects it into the quantum well when the proper control signal is applied. In general, there are several ways to control the quantum structure: (1) using electric signals only, (2) using magnetic signals only, or (3) using a combination of electric and magnetic signals. The electric control signal preferably has specified amplitude levels (Vlow/Vhigh) and given pulse width. The magnetic control signal is preferably of appropriate strength.

Note that the magnetic field control can be used to select an electron with a given spin orientation. This uses the property of electrons to orient their spin depending on the direction of the magnetic field direction at the time when the single electron was isolated from the classic sea of electrons. The direction of the magnetic field can be changed and thus the two spin orientations can be individually selected.

In order to perform a quantum operation in a given quantum structure having two or more qdots, the quantum system first needs to be initialized into a known base state. One or more electrons can be injected into the multi-qdot quantum structure. These single electrons are injected only into some of the qdots of the overall quantum structure. Next, control imposing signals are applied that determine the quantum evolution of the state and perform a certain desired quantum operation.

In general, the quantum operation performed depends on the specific control signals applied. In the case of a single position/charge qubit including two qdots that can realize a generalized phase rotation of the quantum state, the rotation angle is dependent on the pulse width of the control signal applied as compared to the Rabi (or occupancy state) oscillation period.

In a two qdot quantum system, if the tunneling barrier is lowered and kept low, a quantum particle starting from one of the qdots will begin tunneling to the next qdot. At a given time of half the Rabi oscillation period the particle will be completely on the second qdot, after which it will start tunneling back to the first qdot. At a certain time, the particle will have returned to the first qdot, after which the process repeats itself. This process is called the Rabi or occupancy oscillation and its period is named the Rabi or occupancy oscillation period. The phase rotation in a two qdot system will depend on the control signal pulse width as related to the Rabi oscillation period.

A diagram illustrating an example initialization configuration for a quantum interaction structure using tunneling through a local depleted region in a continuous well is shown in FIG. 36. The circuit comprises a classic well 1110, single particle (e.g., electron) injector circuit 1112, quantum well 1114, and control gate 1118. The quantum structure comprises two qdots (additional qdots are possible) on either side of the control gate 1118, and a tunneling path (represented by the arrow) that has a partial overlap with the qdots. The quantum operation is controlled by a control gate (or control terminal) 1118 situated in close proximity of the tunneling path.

In one embodiment, the qdots are implemented by semiconductor wells, while the tunneling path is realized by a polysilicon layer that partially or completely overlaps the two wells. The tunneling appears vertically over the thin oxide layer between the semiconductor well and the polysilicon layer. The control terminal is realized with another well or another polysilicon layer placed in close proximity in order to exercise reasonable control over the tunneling effect.

In another embodiment, a semiconductor quantum processing structure is realized using lateral tunneling in a local depleted well. The two qdots are linked by a region that is locally depleted where the tunneling occurs (represented by the arrow). The control terminal typically overlaps the tunneling path in order to maintain well-controlled depletion of the entire linking region between the two qdots. This prevents direct electric conduction between the two qdots.

In another embodiment, the two qdots of the quantum structure are realized by a single semiconductor well having a control polysilicon layer on top. The tunneling occurs laterally/horizontally through the depleted region that isolates the two qdots.

It is noted that quantum structures can be implemented in semiconductor processes using various tunneling effects. One possible tunneling is the through a thin oxide layer. In most semiconductor processes the thinnest oxide is the gate oxide, which can span several atomic layers. In some processes, the oxide layer used by the metal-insulator-metal (MIM) capacitance is also very thin. Another example is the tunneling through a depleted region between two semiconductor well regions. Such a local depleted region may be induced by a control terminal into an otherwise continuous drawn well or fin.

A diagram illustrating an example planar semiconductor quantum structure using tunneling through oxide layer is shown in FIG. 37A. The semiconductor qubit, generally referenced 1120, comprises two qdots 1124, 1128, partial overlapped polysilicon gate 1129 and vertical thin oxide tunneling 1126, and can contain a particle 1122.

A diagram illustrating an example planar semiconductor quantum structure using tunneling through local depleted well is shown in FIG. 37B. The semiconductor qubit, generally referenced 1130, comprises two qdots 1134, 1138, control gate 1139, and horizontal local depleted well tunneling 1136, and can contain a particle 1132.

Note that there are numerous types of semiconductor processes. Some are planar, while others are used to fabricate 3D structures (e.g., FinFET). A diagram illustrating an example 3D process semiconductor quantum structure using tunneling through oxide layer is shown in FIG. 37C. The semiconductor qubit, generally referenced 1140, comprises two qdots 1142, 1143, control gate 1145, 3D fins 1146, 1141, and partial fin-to-gate overlap and vertical thin oxide tunneling 1148, and can contain a particle 1144.

A diagram illustrating an example 3D process semiconductor quantum structure using tunneling through local depleted well is shown in FIG. 37D. The 3D semiconductor qubit, generally referenced 1150, comprises two qdots 1154, 1153, control gate 1155, 3D fins 1156, 1151, and horizontal local depleted fin tunneling 1158, and can contain a particle 1152.

In one embodiment, controlled-NOT (CNOT) quantum gates can be realized with any of the above described qubit structures implemented in either planar or 3D semiconductor processes.

A diagram illustrating an example CNOT quantum interaction gate using tunneling through oxide layer implemented in planar semiconductor processes is shown in FIG. 38A. The quantum interaction gate comprises two qubits, qubit A and qubit B, with each qubit comprising two qdots 1166, 1163, tunneling path 1161, and control terminal 1168. Qdots 1 and 2 of qubit A and qdots 3 and 4 of qubit B are arranged such that qdots 2 and 3 are close enough for (possibly present there) particles 1164 to interact, for example, in an electrostatic manner.

A diagram illustrating an example CNOT quantum interaction gate using tunneling through local depleted well implemented in planar semiconductor processes is shown in FIG. 38B. The quantum interaction gate comprises two qubits, qubit A and qubit B, with each qubit comprising two qdots 1186, 1183, tunneling path 1188, and control terminal 1181. Qdots 1 and 2 of qubit A and qdots 3 and 4 of qubit B are arranged such that qdots 2 and 3 are close enough for particles 1184 to interact.

A diagram illustrating an example CNOT quantum interaction gate using tunneling through oxide layer implemented in 3D semiconductor processes is shown in FIG. 38C. The quantum interaction gate comprises two qubits, qubit A and qubit B, with each qubit comprising two qdots 1174, 1177, tunneling path 1171, 1173, 1175, and control terminal 1178. Qdots 1 and 2 of qubit A and qdots 3 and 4 of qubit B are arranged such that qdots 2 and 3 are close enough for particles (if present there) 1176 to interact.

A diagram illustrating an example CNOT quantum interaction gate using tunneling through local depleted fin implemented in 3D semiconductor processes is shown in FIG. 38D. The quantum interaction gate comprises two qubits, qubit A and qubit B, with each qubit comprising two qdots 1192, 1198, tunneling path 1196, and control terminal 1194. Qdots 1 and 2 of qubit A and qdots 3 and 4 of qubit B are arranged such that qdots 2 and 3 are close enough for particles 1190 to interact.

Quantum Interaction

Quantum computing is based on the interaction between two or more individual particles that have been separated from a collectivity and which follow the laws of quantum mechanics. In order for two particles to interact, they generally need to be brought in close proximity. Particles that are relatively far away from one another have a small or negligible interaction.

Each particle carries information in its position and/or spin. Position/charge qubit based quantum computing uses the position to encode information, while spin qubit based quantum computing uses the spin of the particles to encode information. Hybrid qubits use both the position and the spin to encode information.

The two or more particles that need to interact and thus make an exchange of information need to be separately initialized in their corresponding quantum state. The separation may be either in distance, ensuring a negligible interaction of the particles as they are initialized, or in time when the particles are initialized at different time instances. In some embodiments both space and time separation may be used to ensure isolation between the two or more starting quantum states.

When two or more quantum particles/states are brought in close proximity, they interact with one another and in the process exchange information. We call the particles entangled as each of the particles carry information from all particles that have interacted. After the entanglement has occurred, the particles are moved at large distance and they still carry the entire information contained initially by the distinct initialized states. If measurement/detection is performed on one of the particles from the entangled ensemble, the corresponding quantum state will be collapsed. By measuring, for example, a charge qubit it is determined whether the particle is present or not in a given qdot. When one qubit is measured the corresponding component from the other qubits that are part of the entangled ensemble will also collapse.

In the case of semiconductor quantum structures based on tunneling through a local depletion region induced in a continuous well under the control of a gate terminal, the tunneling current is the quantum physics effect that governs the operation of the structure. The tunneling effect/current is dependent on one side on the tunnel barrier height, which in turn depends on the signal level applied at the control terminal. A second element that impacts the tunnel barrier and thus the tunneling effect is the presence of any other particle (one or more) in proximity of the target qubit. The presence or absence of another particle will change the Rabi oscillation frequency of a given target qubit. In a double qdot system when the control terminal determines a lowering of the tunnel barrier, the quantum particle will start tunneling forth and back between the two qdots. The precise position of the particle will depend on the pulse width of the control signal that enables the Rabi oscillation.

In order to get interaction between two particles present in their respective qubits, a semiconductor system with at least four qdots is needed. There are multiple ways of operating a two qubit quantum structure, depending on how and what control signals are applied. In one embodiment of the quantum interaction gate, one of the two qubits may be designated as the “target” qubit and the other as the “control” qubit. The state evolution of the target qubit will be impacted by the state of the control qubit. The control qubit stays fixed during the interaction and only the target qubit will change its measured state. In the interaction process, however, both particles will entail changes as a result of their entanglement. In the position/charge qubit implementation, the spin of the control qubit may change as a result of the interaction, while the position of the target qubit will change as a result of the interaction. Any combination of position and spin changes are possible for the target and control qubits. In this embodiment, only the target qubit control terminal receives a pulse. Various quantum gates can be constructed in this way, including the controlled-NOT quantum gate, the Toffolli (control-control-NOT) quantum gate, the controlled rotation quantum gate, and the ancillary quantum gate.

Moving the quantum particles/states to and from given quantum gates is performed with quantum shift registers. Their length and orientation are preferably such that it links the different quantum gates into a corresponding quantum circuit based on a particular quantum algorithm.

In yet another embodiment of the quantum interaction gate, both (or all) qubits are allowed to change in their measured state (position, spin, or both). To achieve this both (or all) control terminals are pulsed. As a result, both (or all) particles that enter entanglement will have their measured state changed (position, spin, or both). As a byproduct of the entanglement, the other non-measured dimension may experience changes as well, e.g., the spin in a position qubit or the position in a spin qubit.

In real life implementations of such semiconductor quantum gates/structures, there are process variations (e.g., distances, thicknesses, dimensions, etc.) and also variability of the control signals (e.g., pulse width variabilities) which result in different amounts of Rabi oscillation period modifications. In one embodiment, a calibration procedure of the semiconductor quantum gate is applied to achieve CNOT functionality. An advantage of the semiconductor quantum implementation is that the integrated circuits approach allows the individual calibration of each quantum gate in the system. This compensates both for the random and the deterministic components of the variability.

A diagram illustrating a first example of semiconductor entanglement quantum interaction gate including initialization, staging, interaction, and output locations is shown in FIG. 39. The quantum interaction gate, generally referenced 1240, in the shape of double V comprises two qubits in close proximity and gradual increasing of the distance between the staging and initialization/detection or output locations to minimize parasitic interaction. Other shapes are also possible, while achieving large distance when interaction is not desired and close distance when interaction is desired. Interaction occurs between the two interaction qdots 1243, 1244.

A diagram illustrating an example semiconductor double qdot qubit using tunneling through a separate layer planar structure is shown in FIG. 40A. The planar semiconductor qubit, generally referenced 1430, uses thin gate oxide tunneling and comprises qdots 1434, 1438, control gate 1432, and polysilicon or oxide 1436.

A diagram illustrating an example planar semiconductor double qdot qubit using tunneling through a local depleted well planar structure is shown in FIG. 40B. The planar semiconductor qubit, generally referenced 1440, uses tunneling 1448 through a local depletion region inside a continuous well, and comprises qdots 1444, 1441, control gate 1446, and contact 1442.

A diagram illustrating an example 3D semiconductor qubit using tunneling through a separate gate oxide layer 3D FIN-FET structure is shown in FIG. 40C. The 3D semiconductor qubit with fin-to gate tunneling 1471, generally referenced 1450, comprises qdots 1454, 1456, fins 1458, and control gate 1452.

A diagram illustrating an example 3D semiconductor qubit using tunneling through a local depletion in a fin structure is shown in FIG. 40D. The 3D semiconductor qubit with local depleted fin tunneling 1473, generally referenced 1451, comprises qdots 1453, 1455, fins 1459, and control gate 1457.

A diagram illustrating a semiconductor CNOT quantum interaction gate using two qubit double qdot structures with tunneling through a separate planar structure is shown in FIG. 40E. The CNOT quantum interaction gate, generally referenced 1460, comprises a first qubit having a plurality of qdots 1466, control gate 1464, and metal layer 1462 above the control gate 1464. A second qubit comprises a plurality of qdots 1465, control gate 1463, and contact 1467. The two qubits are located in close proximity so that interaction occurs between qdots 1468 and 1461. Other interactions may occur as indicated by the arrows but these are much weaker since the qdots are further away from each other.

Semiconductor CNOT gates can be built using tunneling through a depletion region. Several different positions for getting interaction between two or more particles inside the same continuously drawn well will now be described. In this case, the two interacting particles are not on separate chain structures, but inside the same chain structure.

A diagram illustrating a first example quantum interaction gate with interaction between two particles in the same continuous well is shown in FIG. 40F. The quantum interaction gate, generally referenced 1470, comprises a plurality of qdots in the same continuous well, two particles 1476, 1478, and control gates 1472, 1474. Since the two particles are separated by the top qdot, the interaction in this example is weaker.

A diagram illustrating a second example quantum interaction gate with interaction between two particles in the same continuous well is shown in FIG. 40G. The quantum interaction gate, generally referenced 1480, comprises a plurality of qdots in the same continuous well, two particles 1486, 1488, and control gates 1482, 1484. Since the two particles are in adjacent qdots, the interaction in this example is stronger.

A diagram illustrating a third example quantum interaction gate with interaction between two particles in the same continuous well is shown in FIG. 40H. The quantum interaction gate, generally referenced 1490, comprises a plurality of qdots in the same continuous well 1491, two particles 1496, 1498, and control gates 1494. Since the two particles are in adjacent parallel qdots, the interaction in this example is the strongest.

In an alternate embodiment the two particles that will interact can be hosted by two different chain structures. A diagram illustrating a first example quantum interaction gate with interaction between two or more particles in different continuously drawn wells is shown in FIG. 40I. The quantum interaction gate, generally referenced 1500, comprises two qubits with shared control gates 1502, and two particles 1506, 1508. The qubits are located in close proximity to permit strong interaction between the particles.

A diagram illustrating a second example quantum interaction gate with interaction between two particles in different continuous wells is shown in FIG. 40J. The quantum interaction gate, generally referenced 1510, comprises two qubits with separate control gates 1512, 1514 and two particles 1516, 1518. The qubits are not located in close proximity thus resulting in a weaker interaction between the particles.

A diagram illustrating a second example quantum interaction gate with interaction between two particles in different continuous wells is shown in FIG. 40K. The quantum interaction gate, generally referenced 1520, comprises two qubits with shared control gates 1522, 1524 and two particles 1526, 1528. Although the qubits are located in close proximity, the particles are not in adjacent qdots thus resulting in a weaker interaction between the particles.

A diagram illustrating a second example quantum interaction gate with interaction between two particles in different continuous wells is shown in FIG. 40L. The quantum interaction gate, generally referenced 1530, comprises two qubits each with separate control gates 1532, 1534, and two particles 1536, 1538. Although the qubits are located at the pinnacle of their respective V structures, the two qubits are skewed from each other thus resulting in weaker interaction between the particles.

A diagram illustrating an example quantum interaction gate with continuous well incorporating reset, inject, impose, and detect circuitry is shown in FIG. 41. The quantum interaction gate, generally referenced 1590, comprises a continuous well 1598 with a plurality of control gates 1599, 1601, depletion regions 1600, interfaces 1596, 1602 to classic circuitry, reset circuit 1591, injector circuit 1592, imposer(s) circuits 1593, and detector circuit 1594. In this case, the imposers that isolate the adjacent qdots overlap the folded side of the continuous well.

A diagram illustrating an example double V CNOT quantum interaction gate using common control gates for sections in closer proximity to permit smaller spacing and stronger interaction is shown in FIG. 42. The quantum interaction gate, generally referenced 1620, comprises two qubits arranged in a double V configuration. Each qubit comprising a continuous well 1621 divided into a plurality of qdots by common control gates 1623 having contacts 1624 and separate control gates 1626 having contacts 1627, interface 1622 to classic circuitry, and interaction qdot 1625. The two qubits use tunneling through local depleted well and shared control gates that result in closer placement and thus stronger interaction.

Controlled-NOT and higher order quantum gates realized in planar semiconductor processes have been disclosed supra. Similar quantum structures can be realized in three-dimensional semiconductor processes. A diagram illustrating a first example CNOT quantum interaction gate using 3D FIN-FET semiconductor process with tunneling through separate layer and interaction from enlarged well islands allowing smaller spacing and stronger interaction is shown in FIG. 43A. The quantum interaction gate, generally referenced 1720, comprises two qubits each including a plurality of qdots 1721, 1724, control gates 1723 and 3D FIN FET structures 1722. A complete overlap between gate and fin-well was used.

By reducing the overlap between gate and fin-well the overall capacitance of the structure is reduced, increasing the Coulomb blockade voltage. A diagram illustrating a second example CNOT quantum interaction gate using 3D FIN-FET semiconductor process with tunneling through separate oxide layer, partial overlap between gate and fin-well, and interaction from enlarged well islands allowing smaller spacing and stronger interaction is shown in FIG. 43B. The quantum interaction gate, generally referenced 1730, comprises two qubits each including a plurality of qdots 1731, 1734, control gates 1733 and 3D FIN FET structures 1732. The interaction is realized between enlarged well islands allowing a smaller spacing and thus a stronger interaction.

Semiconductor quantum interaction gates can be realized in 3D processes using tunneling through fin local depletion regions induced in semiconductor fins. A diagram illustrating a third example CNOT quantum interaction gate using 3D FIN-FET semiconductor process with interaction from enlarged well islands allowing smaller spacing and stronger interaction is shown in FIG. 43C. The quantum interaction gate, generally referenced 1740, comprises two qubits each including a plurality of qdots 1742, 1748, control gates 1746 and 3D FIN FET structures 1744. Note that for CNOT function two semiconductor chains are implemented. For higher order gates more than two semiconductor chains can be used.

Interaction between wells can result in tighter spacing and thus stronger interaction between quantum particles. Interaction, however, can be achieved between particles located in semiconductor fins. A diagram illustrating a fourth example CNOT quantum interaction gate using 3D FIN-FET semiconductor process with fin to fin interaction mandating larger spacing resulting in weaker interaction is shown in FIG. 43D. The quantum interaction gate, generally referenced 1750, comprises two qubits each including a plurality of qdots 1752, 1758, control gates 1756 and 3D FIN FET structures 1754.

It is noted that the majority of the quantum structures disclosed herein are a subset of a general class of quasi-unidimensional quantum cells. In a quasi-unidimensional quantum structure the quantum action occurs locally for each pair of adjacent quantum dots on a given direction. The action can be horizontal, vertical, any other angle, in two dimensions, or in three dimensions. In three dimensions a line is needed where the quantum operation occurs predominantly along that line referred to as a chord line. In contrast, multi-dimensional tunneling is problematic because it results in multiple energy levels which results in complex quantum behavior. The chord line is a quasi-unidimensional path that the particle can evolve in a three dimensional structure. Note that any circuit fabricated using a semiconductor process is in reality a 3D structure. In this case, however, the quantum particle evolves substantially along the unidimensional path of the chord line.

A diagram illustrating an example qdot with multidimensional tunneling and multiple clusters of energy levels is shown in FIG. 44A. The qubit, generally referenced 2000, comprises a pair of quantum dots 2004, control terminal 2002, and tunneling path 2006 between the qdots. Note that the qdots can have any shape and use any process as described supra. Arrows 2008 denote the multidimensional tunneling which is undesirable. The associated energy graph shows multiple clusters of energy levels in two bands 2001, 2003. Having multiple energy levels results in more complicated Hamiltonian. The level of complexity of the behavior of the circuit rises to a point where it is very difficult to utilize. A 3D structure, for example, is practically unusable due to the complexity and difficulty in controlling the structure using analog electronic control.

If the width of the tunneling path is relatively large, the tunneling can occur in multiple directions, which is undesirable. Each of the individual tunneling paths create their own specific two-level energy system. Preferably, a two qdot qubit has a two energy level system. With multiple tunneling paths, however, each path has slightly different barriers for tunneling, because the distances are different for each different path. The result is an energy system having multiple clusters as shown in FIG. 44A.

Note that although a single particle travels between the qdots, it is not known which path the particle will take in the multidimensional tunneling. Each path has its own two level system. Thus, it cannot be predicted with precision what the level of energy which means that it is difficult to determine the potential to apply to control the qubit to get a specific tunneling. This is very problematic because it means there are always multiple solutions for the control thus making it relatively undefined.

A diagram illustrating an example qdot with unidimensional tunneling and two well separated energy levels is shown in FIG. 44B. The qubit, generally referenced 2010, comprises a pair of quantum dots 2014, control terminal 2012, and tunneling path 2016 between the qdots. Note that the qdots can have any shape and use any process as described supra, e.g., semiconductor wells, etc. Arrow 2018 denotes the desirable unidimensional tunneling. The associated energy graph shows two energy levels 2011, 2013.

To achieve a precise two level energy system the tunneling path cannot vary over a wide range. This is achieved using one-dimensional tunneling where there is largely a single path that the particle can take (i.e. a unidirectional or unidimensional path). In addition, there is a single tunnel barrier for this path corresponding to the single two state level. The unidimensional (i.e. narrow) tunneling path that the particle is permitted to take or evolve is referred to as a chord line. The chord line can have any desired shape or configuration in 2D or 3D space. Having a unidimensional tunneling path provides clear separation of the energy levels and results in simpler control of the qubit.

It is noted that ideally unidimensional tunneling is desired but in reality it is difficult if not impossible to achieve due to the extremely narrow dimension required for the tunneling path which is not practical to fabricate. Thus, in reality, quasi-unidimensional tunneling is achievable where the tunneling path is concentrated in a particular area or in a channel having a finite width where the energy levels will be at a given level.

Note also that quasi-unidimensional tunneling is acceptable as long as the separation of the energy levels is substantially larger than any kind of level variation due to the wider tunneling path. This is not the case in the energy level diagram in FIG. 44A where the separation of the energy levels is comparable with the variation of the level.

Note further that quasi-unidimensional tunneling means that the quantum evolution of the particle occurs in a fairly narrow region around a unidimensional direction. The arrangement of pairs of quantum dots which may be in any direction, with bifurcations, etc. make up a chord line. The chord line is a narrow channel over which the quantum particle can evolve in the structure. Either the particle will not be outside the chord line or the probability of the particle being outside the chord line or narrow channel of evolution is so small that it is negligible and does not significantly impact the quantum cell operation.

A diagram illustrating an example double qdot structure with full overlap of the control gate over the quantum wells is shown in FIG. 45A. The quantum structure, generally referenced 2060, comprises a pair of qdots 2062, i.e. quantum wells #1 and #2, and control gate or tunneling barrier 2064. Each qdot can have any desired shape as described supra. In addition, the qubit can be extended to any number of qdots.

This quantum structure is an example of tunneling through depletion region induced in a well and having full overlap of the control gate 2064 over the quantum wells 2062. In this case, the tunneling (arrows 2066) occurs over the entire width 2068 of the well. This, however, results in large capacitance values and thus low Coulomb blockade voltages which make the structure difficult to control using classic electronics. The wide tunneling path results in the problem of multiple tunneling paths described supra which results in multiple energy levels. To reduce the Coulomb blockade voltage, the tunneling must be constrained to a smaller aperture. Thus, what is desirable is a very narrow chord line tunneling path between the pair of qdots, i.e. the tunneling path needs to be quasi-unidimensional. This results in relatively easy and predictable control of the quantum structure.

A diagram illustrating example double qdot structure with controlled tunneling between two quantum wells is shown in FIG. 45B. A diagram illustrating variation of potential in a double qdot structure with controlled tunneling between the two quantum wells is shown in FIG. 45C. The quantum structure, generally referenced 2070, comprises a pair of qdots 2072, i.e. quantum wells #1 and #2, and control gate or tunneling barrier 2074. Each qdot can have any desired shape as described supra. In addition, the qubit can be extended to any number of qdots.

In operation, the particle 2084 injected into one of the quantum wells will not be able to move if the tunneling barrier 2080 is high. Once the control gate allows the lowering of the tunnel barrier 2082, the particle starts tunneling from one well to the other. If the barrier is maintained low, a Rabi (occupancy) oscillation is established, whereby the particle tunnels back and forth from one well to the other. The Rabi oscillation stops when the tunnel barrier is raised.

In this case, the tunneling path or aperture 2078 the particle is forced to travel in is significantly narrowed. This results in quasi-unidimensional tunneling for the particle between the two quantum wells.

A diagram illustrating an example quantum structure using tunneling through thin oxide with full overlap of the gate over the quantum wells is shown in FIG. 46A. The quantum structure, generally referenced 2090, comprises qdot 2092 and qdot 2096 separated by a fully overlapping control gate 2094. In this structure, the gate is isolated from the wells by a thin oxide layer through which the tunneling occurs.

The large gate overlap results in large apertures 2091, 2093, multipath tunneling and large capacitance values and thus low Coulomb blockade voltages which are hard to control using classical electronics. What is desired, however, is to constrain the tunneling path as much as possible in order to constrain the energy levels. To constrain the tunneling path, it must be made narrower so that the particle is constrained to a very narrow path that can be described as unidimensional.

As the overlap between the gate and the well is reduced, the problem transforms from a two dimensional or three dimensional problem into a more desirable and simpler unidimensional problem. A diagram illustrating an example quantum structure using tunneling through thin oxide with partial overlap on the edge of the gate over the quantum wells is shown in FIG. 46B. The quantum structure, generally referenced 2100, comprises a pair of qdots 2102, 2104 separated by a partially overlapping control gate 2106.

In this example, the partial overlap of the gate on the edge of the qdots results in lower capacitance values and thus higher Coulomb blockade voltages, which are easier to control with classic electronics. Restricting the tunneling path to a smaller aperture 2101, 2103 and making it more unidimensional increases the Coulomb voltage. The size of the aperture is preferably much smaller than the dimensions of the quantum well itself.

A diagram illustrating an example quantum structure using tunneling through thin oxide with partial overlap on the corners of the gate over the quantum wells is shown in FIG. 46C. The quantum structure, generally referenced 2097, comprises a pair of qdots 2098, 2108 separated by a partially overlapping control gate 2107.

In this example, the partial overlap of the gate on the corners of the qdots results in even lower capacitance values and thus higher Coulomb blockade voltages, which are easier to control with classic electronics. Restricting the tunneling path to an even smaller aperture 2099, 2105 and making it even more unidimensional further increases the Coulomb voltage.

A diagram illustrating a general tunneling path implementation between two quantum dots is shown in FIG. 47A. The quantum structure, generally referenced 2150, comprises a pair of quantum dots 2152, qdot #1 and qdot #2, coupled by a tunneling path 2154 which is controlled by a tunneling control 2156. Each quantum dot can have any desired shape. The tunneling path is the path that the particle takes from one qdot to another qdot. When implemented in a planar semiconductor process, the tunneling path may comprise polysilicon, metal, thin oxide, or a depletion well. Tunneling control may be direct electrical potential or nearby imposing layer to generate an electrostatic field either by a separate layer or another qdot (e.g., imposer quantum dot). In all cases, the tunneling path is quasi-unidimensional to form a chord line.

A diagram illustrating a polysilicon tunneling path implementation between two quantum dots is shown in FIG. 47B. The quantum structure, generally referenced 2160, constructed using a planar semiconductor process, comprises a pair of quantum wells or qdots 2162, qdot #1 and qdot #2, coupled by a tunneling path 2164 which is controlled by a tunneling control (not shown for clarity). In this embodiment, the tunneling path is constructed from thin oxide and polysilicon layer.

A diagram illustrating a metal tunneling path implementation between two quantum dots is shown in FIG. 47C. The quantum structure, generally referenced 2170, constructed using a planar semiconductor process, comprises a pair of quantum wells or qdots 2172, qdot #1 and qdot #2, coupled by a tunneling path 2174 which is controlled by a tunneling control (not shown for clarity). In this embodiment, the tunneling path is constructed from thin oxide and metal layer.

A diagram illustrating a local depletion tunneling path implementation between two quantum dots is shown in FIG. 47D. The quantum structure, generally referenced 2180, constructed using a planar semiconductor process, comprises a pair of quantum wells or qdots 2182, qdot #1 and qdot #2, coupled by a tunneling path 2186 which is controlled by a control gate 2184 providing local depletion control. In this embodiment, the tunneling path is diffusion well with induced depletion region.

A diagram illustrating a first polysilicon tunneling path implementation between two quantum dots using a 3D process is shown in FIG. 48A. The quantum structure, generally referenced 2190, constructed using a 3D semiconductor process, comprises a pair of semiconductor fins 2192, qdot #1 and qdot #2, coupled by a tunneling path 2194 which is controlled by a control gate (not shown). In this embodiment, the tunneling path is thin oxide and polysilicon layer.

A diagram illustrating a second polysilicon tunneling path implementation between two quantum dots using a 3D process is shown in FIG. 48B. The quantum structure, generally referenced 2200, constructed using a 3D semiconductor process, comprises a pair of semiconductor fins 2202, qdot #1 and qdot #2, coupled by a tunneling path 2204 which is controlled by a control gate (not shown). In this embodiment, the tunneling path is thin oxide and polysilicon layer.

A diagram illustrating a metal tunneling path implementation between two quantum dots using a 3D process is shown in FIG. 48C. The quantum structure, generally referenced 2210, constructed using a 3D semiconductor process, comprises a pair of semiconductor fins 2212, qdot #1 and qdot #2, coupled by a tunneling path 2214 which is controlled by a control gate (not shown). In this embodiment, the tunneling path is thin oxide and metal layer.

A diagram illustrating a local depletion tunneling path implementation between two quantum dots using a 3D process is shown in FIG. 48D. The quantum structure, generally referenced 2220, constructed using a 3D semiconductor process, comprises a pair of semiconductor fins 2222, qdot #1 and qdot #2, coupled by a tunneling path 2226 which is controlled by a control gate 2224 providing local depletion control. In this embodiment, the tunneling path is a diffusion well with induced depletion region.

Note that to achieve quantum operation particles need to be able to move from one quantum well to another. This is achieved by tunneling of the particle. The tunneling probability depends on the height of the tunneling barrier, which in turn can be modified by a control signal. The control signal can be an electric signal or a magnetic signal or an electromagnetic signal. Tunneling between two semiconductor wells can be done through a thin oxide layer or through a thin local depletion region.

A diagram illustrating a cross section of a planar semiconductor process of a quantum structure with tunneling through depletion region and metal tunneling control is shown in FIG. 49A. The quantum structure, generally referenced 2230, comprises a substrate 2232, oxide layer 2234, well 2236 for horizontal tunneling, thin oxide 2238, polysilicon control gate 2240, optional electrical contact 2244, metal imposer (tunneling control) 2242, and alternate imposer (tunneling control) 2246. The quasi-unidimensional tunneling path 2248 provides a path for a particle to travel from one qdot to the other.

The depletion region induced in the well by the control gate 2240 has a thickness that is dependent on the signal applied to the control gate. This thickness is relatively small to allow a large tunnel current. This ensures a higher frequency Rabi oscillation between two quantum wells.

A diagram illustrating a cross section of a planar semiconductor process of a quantum structure with tunneling through thin oxide layer and metal tunneling control is shown in FIG. 49B. The quantum structure, generally referenced 2250, comprises a substrate 2252, oxide layer 2254, wells 2256, thin oxide 2258, polysilicon gate tunneling path 2260, and metal control gate (tunneling control) 2262. The tunneling path 2266 provides a path 2266 for a particle to travel from one qdot to the other.

The tunneling occurs through thin oxide via well to gate tunneling with tunneling current provided by the metal control gate 2262. The structure is generally isolated from surrounding layers using thicker oxide. Tunneling through the thick oxide layer is negligible. Therefore, the particle moves only via tunneling through the thin oxide layer (arrow 2266). The tunneling path includes: (1) a first vertical tunneling between the left quantum well and the gate; (2) the polysilicon tunneling path; and (3) a second vertical tunneling between the gate and the right quantum well.

A diagram illustrating quasi-unidimensional vertical tunneling is shown in FIG. 50A. The charge-qubit quantum structure, generally referenced 2270, comprises two pairs of 3D quantum dots 2272 where tunneling path 2276 travels vertically from well to oxide 2274 and then oxide to well. These quantum dots comprise vertical fins in a third Z dimension semiconductor layer where vertical tunneling is combined with horizontal transport. Tunneling in this structure is similar to that of the structure described supra where the quasi-unidimensional tunneling occurs between two fins and may go through either polysilicon, metal, thin oxide, or the fin itself.

A multidirectional tunneling path is achievable in the 3D process which has both horizontal and vertical segments. This is an advantage of the three dimensional process. The particle can not only move in the XY plane but also Z dimension which is where it goes from well to oxide, through the polysilicon, and then vertical again to the well providing quasi-unidimensional tunneling in XYZ dimensions,

A diagram illustrating quasi-unidimensional horizontal tunneling is shown in FIG. 50B. The quantum structure, generally referenced 2280, comprises a pair of 3D quantum dots 2282, and thin oxide 2286. Tunneling path 2284 travels horizontally from one region of a well to another through an induced depletion region in the semiconductor fin. Notwithstanding the 3D structure, this structure essentially operates in the XY plane since tunneling occurs in a single plane. The structure can be oriented in any position in the plane of the process.

A diagram illustrating a planar semiconductor process cross section with polysilicon tunneling path and several control options is shown in FIG. 51A. The quantum structure comprises two quantum dots (e.g., one charge qubit) using tunneling through thin oxide layer and control from either a polysilicon or metal terminal. The cross section, generally referenced 2290, comprises substrate 2292, oxide 2294, shallow trench isolation (STI) oxide 2300, imposer well 2309, quantum well 2308, back end of line (BEOL) 2296, thin oxide 2306, polysilicon tunneling path layer 2304, imposer control gate 2302, alternate metal imposer layer 2298, particle 2305, and sparse dopants 2307. The control options in this structure include the potential imposing polysilicon gate layer 2302, the potential imposing metal gate layer 2298, or potential imposing well 2309.

In one embodiment, an electrical field applied to the quantum transport path is operative to control a tunneling barrier of a quantum particle through preferential tunneling paths. In operation, a distant control terminal creates an electrical field that couples to the floating gate and changes its potential. The potential change is indirect. The floating gate must be ac-coupled or Coulomb-coupled.

A diagram illustrating a planar semiconductor process cross section with metal tunneling path and control is shown in FIG. 51B. The quantum structure comprises two quantum dots (e.g., one charge qubit) using tunneling through thin oxide layer and control from either a polysilicon or metal terminal. The cross section, generally referenced 2380, comprises substrate 2382, buried oxide 2384, shallow trench isolation (STI) oxide 2386, quantum wells 2388, back end of line (BEOL) 2390, thin oxide 2394, metal tunneling path layer 2396, metal imposer layer 2392, particle 2391, and sparse dopants 2398.

Note that in the FinFET semiconductor processes, tunneling allows the movement of the quantum particle through thin oxide layer and through thin local depletion region. A diagram illustrating a 3D semiconductor process cross section with different control options is shown in FIG. 51C. The 3D quantum structure comprises a 3D (e.g., FinFET) semiconductor process implementation of a two quantum dot structure (e.g., charge qubit) using tunneling through thin oxide layer and control from a metal terminal. The quantum structure comprises two quantum dots (e.g., charge qubit) using tunneling through thin oxide layer and control from either a polysilicon or metal terminal. The cross section, generally referenced 2310, comprises substrate 2312, oxide 2314, semiconductor fin 2320, gate oxide 2322, gate 2324, imposer control gate 2318, alternate imposer metal layer 2316, imposer fin 2329, thin oxide 2326, particle 2321, and sparse dopants 2327. The control options in this structure include the potential imposing polysilicon gate layer 2318 or the potential imposing metal gate layer 2316.

It is noted that the unidimensional tunneling action can occur over several types of layers that may comprise polysilicon, metal, or induced depletion well. In one embodiment, the polysilicon, metal, and wells are at different levels in the cross section of the semiconductor process. All, however, exhibit unidimensional tunneling action. Thus, for each pair of qdots there is predominantly one line (i.e. chord line) over which the quantum operation happens which may comprise a variety of types of layers. In the case of multiple qdots, each pair may extend in different directions.

To control the tunneling of the evolution of the particle in the chord line, an electrostatic field is applied such as via a potential which is varied to raise and lower the tunneling barrier. In one embodiment, for a planar or 3D process, the potential is impacted via a metal layer, a control gate layer, polysilicon layer, or from another well in proximity.

A diagram illustrating carrier energy level distribution at room temperature and cryogenic temperatures is shown in FIG. 52. The energy distribution 2342 at room temperature is essentially in two continuous energy bands. Two electrons can occupy each energy level: one with spin up and one with spin down orientation. At cryogenic temperature, however, the energy levels 2340 are discrete with energy splitting between the levels of spin-up and spin-down electrons. This allows the isolation of only a single particle, e.g., electron, to be used in a quantum operation.

As described supra, control of the quantum structure may be via electric field and/or magnetic field. In the presence of a magnetic field, the spin of the particle is split. Regardless of the quantum structure, in the presence of a magnetic field, the spin of the particle, e.g., electron, selected to perform quantum computing will align with the magnetic field. The magnetic field can be generated using an inductor, resonator, or magnet.

The present invention in one embodiment is a semiconductor quantum structure having at least two quantum dots with preferential tunneling direction and an optional quantum transport path for the quantum particle. It is noted that different types of tunneling effects can be used in semiconductor structures. In advanced semiconductor processes with very small feature sizes, the oxide layers are thin enough such that significant tunneling can occur through it. One example of thin oxide layer is the oxide between the gate and the well in a MOS transistor of semiconductor process. Another example of thin oxide layer is the layer between the two plates of metal-insulator-metal (MIM) capacitors.

In semiconductor processes, quantum dots that can hold a quantum particle can be realized using semiconductor wells surrounded by oxide layers. Two semiconductor wells linked by a tunneling path allow the quantum particle to go from one side to the other based on the signal applied to a control terminal. This realizes an elementary double qdot quantum structure. It is very difficult to achieve accurate controlled tunneling if the tunneling occurs on all sides (i.e. in all directions) of the quantum well.

To address these issues, the present invention discloses semiconductor quantum structures having preferential tunneling directions where the tunneling is restricted to a small area resulting in aperture tunneling. The advantage of aperture tunneling is that it constrains the quantum transport to a very narrow path, which can be approximated as a unidimensional problem. The narrow path is termed a chord line along which the quantum operation is performed. FIG. 47A, described supra, illustrates the general principle of an elementary double qdot semiconductor quantum structure 2150 having two quantum wells 2152 using preferential tunneling path direction 2154.

In the case of thin oxide layer tunneling, the two semiconductor wells are placed in close proximity with a thin oxide layer therebetween. FIG. 53 illustrates an example semiconductor structure 2400 using two preferential direction tunneling and a supplementary transport path. The structure comprises two quantum wells 2402, tunneling paths 2406, transport path 2408, and tunneling control 2404. Note that an elementary double qdot structure can be built using more than one tunneling process.

Structure 2400 is an alternative embodiment of an elementary two qdot semiconductor quantum structure comprising two quantum wells (i.e. qdots) using two preferential tunneling directions. In addition, a supplementary transport path 2408 provides quantum particle transport between the locations where tunneling occurs. Examples of layers from the semiconductor process that can be used for transport, include control gate layers or metal layers. The gate may comprise a poly silicon layer (with or without silicide and additional doping), a metal layer, or any combination thereof.

The principles of realizing elementary quantum structures using semiconductor wells, preferential direction tunneling paths, and transport paths can be implemented in many ways, depending on the selected semiconductor process and its features. In addition, both planar and 3D semiconductor processes can be used.

Tunneling between the two semiconductor qdots can be accomplished through a tunneling path that includes an insulator layer. The tunneling, however, must be controlled via a control terminal to implement a controlled quantum structure. In order to achieve preferential tunneling direction, the thickness of the oxide layer surrounding a quantum well may be differentiated. All sides but one of the quantum well have thick oxide layers (or other substantially isolating layers) that block any tunneling. Only one side has a thin oxide layer that allows tunneling.

A diagram illustrating a first example semiconductor structure using preferential tunneling is shown in FIG. 54A. The structure, generally referenced 2410, comprises two semiconductor quantum wells 2412 and tunneling path 2414 under a control gate (not shown). Particles tunnel (indicated by arrow 2416) through a depletion region under the control gate. The two semiconductor wells 2412 are configured with preferential tunneling path therebetween.

A diagram illustrating a second example semiconductor structure using preferential tunneling is shown in FIG. 54B. The structure, generally referenced 2420, is conceptual in nature and might not represent a real quantum structure. The structure comprises two semiconductor quantum wells 2422 and tunneling path 2426 under a control gate (not shown). Particles tunnel (indicated by arrows 2426) through a tunneling path 2424 from one qdot to the other. The two semiconductor wells have a preferential tunneling path at the top. Note that in this example the tunneling path is present on the top and across the two quantum wells.

In another embodiment, a transport path is added. A diagram illustrating a third example semiconductor structure using preferential tunneling is shown in FIG. 54C. The structure, generally referenced 2430, comprises two semiconductor wells 2432 with a quantum transport path 2434 above them and two preferential tunneling paths 2436 between the quantum wells and the quantum transport path. It is noted that this structure is easier to implement in a planar semiconductor process that is capable of fabricating multiple overlapped layers. In this case, there are two tunneling paths 2436 between the quantum wells and the part of the transport path 2434 that overlaps the quantum wells.

In another embodiment, structures with more than two quantum wells can be fabricated, e.g., three, four or more. A diagram illustrating a fourth example semiconductor structure using preferential tunneling is shown in FIG. 54D. The structure, generally referenced 2440, comprises three semiconductor quantum dot wells 2442 with preferential tunneling paths 2444 between them. A diagram illustrating a fifth example semiconductor structure using preferential tunneling is shown in FIG. 54E. The structure, generally referenced 2450, comprises three semiconductor quantum wells 2452 with preferential tunneling paths 2454 on the layer above the quantum wells.

In another embodiment, the tunneling goes through not only an oxide layer, but an intermediate transport path as well. A diagram illustrating a sixth example semiconductor structure using preferential tunneling is shown in FIG. 54F. The structure, generally referenced 2460, comprises three semiconductor quantum dot wells 2462 with preferential tunneling paths 2464 and supplementary quantum transport paths 2466. In this embodiment, a particle can tunnel from a first semiconductor quantum dot through a thin insulator layer to another layer that is conducting. For example, the conducting layer can be the poly silicon gate within which there is particle transport. The particle then tunnels through another insulator layer to a second semiconductor quantum dot.

A diagram illustrating a seventh example semiconductor structure using preferential tunneling is shown in FIG. 54G. The structure, generally referenced 2470, comprises three semiconductor quantum dot wells 2472 with preferential tunneling paths 2474 and supplementary quantum transport paths 2476 with partial overlap between the tunneling path and transport path.

For the quantum structure to be controlled, a control terminal is introduced which is preferably exposed to the tunneling path in order to control it. This is why structures with the tunneling paths as shown in FIGS. 54C, 54F, and 54G are more amenable to implementing the control terminal. Note that the transport path itself may serve as control terminal through its potential level.

There are several ways of implementing semiconductor quantum structures using preferential tunneling direction. Each implementation depends on the features available in a given semiconductor process. A diagram illustrating an example semiconductor well with thin insulation layer on one side and thick insulation on all other sides is shown in FIG. 55. The structure, generally referenced 2480, comprises an oxide material or layer 2482 surrounding an isolated semiconductor well qdot 2483, quantum particle 2484, thin oxide layer or film 2481, control gate/transport path 2486, and a portion of the tunneling path 2488. Note that preferential tunneling can occur on more than one side. In one embodiment, the thin oxide may comprise the gate oxide of a MOS structure, the thick oxide on the side may comprise the trench isolation oxide, and the bottom oxide may comprise the BOX oxide layer of an SOI process that isolates the well from the substrate, although the bottom oxide layer may be missing in some processes. The quantum well/quantum dot is realized by a semiconductor well 2483. Preferably, an undoped well or very lightly doped well is used in order to prevent parasitic interactions with dopant atoms. The top layer above the thin oxide is the gate which can be poly silicon, silicide or metal. In addition, multiple layer gates can also be used. In operation, the tunneling process occurs between the semiconductor well 2483 and the gate 2486 through the thin oxide layer 2481.

In another embodiment, more complex semiconductor quantum structures can be built having two or more quantum dots, i.e. semiconductor wells. A diagram illustrating an example of two semiconductor wells with thin insulation layer on the top and thick insulation on all other sides and a quantum transport path using preferential tunneling direction is shown in FIG. 56. The structure, generally referenced 2490, comprises an oxide material or layer 2492 surrounding two isolated semiconductor well qdots 2493, which may or may not contain a particle 2494, thin oxide layer 2491, control gate/transport path 2496, and tunneling path 2498. Note that preferential tunneling can occur on more than one side. The two separate tunneling paths together with the lateral transport may be also viewed as a single tunneling between the two quantum wells 2493. Note also that the quantum particle 2494 must tunnel through two thin oxide layers 2491 for the transport to complete.

There are several ways to realize the tunneling and transport path that overlaps the semiconductor wells. In addition, the tunneling and transport paths may be realized using diverse layers available in semiconductor processes. Several examples embodiments of planar semiconductor quantum structures using preferential tunneling direction and quantum transport path will now be presented. FIG. 47B shows an example of a structure 2160 with a partially overlapping polysilicon gate 2164. FIG. 577A illustrates an example planar semiconductor structure 2500 with semiconductor well qdots 2502 and a quantum transport path through full overlapping polysilicon gate 2504. FIG. 47C shows an example of a structure 2170 with a partially overlapping metal gate 2174. FIG. 57B illustrates an example planar semiconductor structure 2510 with semiconductor well qdots 2512 and a quantum transport path through full overlapping metal gate 2514. Note that the full overlap of the gate results in larger capacitance of the structure, leading to lower value Coulomb blockade voltages. The partial overlap results in smaller capacitance and thus higher Coulomb blockade voltages, which is advantageous to the implementation of the interface electronic circuits.

Modern 3D semiconductor processes have the advantage of offering narrow semiconductor fins having very small dimensions (e.g., 7, 5, or 3 nm and even 1 nm in the future, or even beyond to sub-1 nm sizes). This results in smaller capacitances and thus higher Coulomb blockade voltages. FIG. 48A shows an example of a 3D semiconductor quantum structure 2190 using preferential tunneling direction and quantum transport path through a partially overlapping polysilicon gate 2194. FIG. 58A illustrates an example 3D semiconductor structure 2520 with semiconductor well qdots 2522 and a quantum transport path through partial overlapping polysilicon gate 2524. FIG. 48C shows an example of a 3D semiconductor quantum structure 2210 using preferential tunneling direction and quantum transport path through a partially overlapping metal gate 2214. FIG. 58B illustrates an example 3D semiconductor structure 2530 with semiconductor well qdots 2532 and a quantum transport path through partial overlapping metal gate 2534.

In general, the semiconductor quantum structures that employ tunneling through thin oxide layer have two or more semiconductor wells and a tunneling and transport path which partially or fully overlaps the semiconductor wells. A separate control terminal imposes the potential on the tunneling and transport path, thus controlling the tunneling in the structure. FIG. 37A illustrates a planar semiconductor quantum structure 1120 using two quantum wells 1124, 1128 and a tunneling path 1126 that is under the control of a control terminal 1129. FIG. 37C shows a 3D semiconductor quantum structure 1140 using two quantum wells 1142, 1143 and a tunneling path 1146, 1148, 1141 that is under the control of a control terminal 1145.

Note that the overlap between the semiconductor well and the gate above may be partial of full in a given direction. A diagram illustrating an example semiconductor quantum structure with full overlap gate layer over the well is shown in FIG. 59A. The structure, generally referenced 2540, comprises thick oxide material or layer 2542 surrounding a quantum well 2544, thin oxide layer 2548, and control gate structure 2546. The structure uses preferential tunneling from the semiconductor well to a gate layer having full overlap over the well.

A diagram illustrating an example semiconductor structure with partial overlap gate layer over the well is shown in FIG. 59B. The structure, generally referenced 2550, comprises thick oxide material or layer 2552 surrounding a quantum well 2554, thin oxide film or layer 2558, and control gate material 2556. The structure uses preferential tunneling from a semiconductor well to a gate layer having partial overlap over the well. Control gate material in this and all other structures disclosed herein may comprise any suitable material, e.g., polysilicon, metal, high-k dielectric, etc.

The control gate layer can be positioned over the quantum well in any number of ways. The top views of several examples of the control gate overlapping the semiconductor well will now be presented. A diagram illustrating an example quantum structure with full center well to gate overlap is shown in FIG. 60A. The structure, generally referenced 2560, comprises a control gate material 2564 fully overlapping quantum well 2562 and possible particle 2566.

A diagram illustrating an example quantum structure with full side well to gate overlap is shown in FIG. 60B. The structure, generally referenced 2580, comprises a control gate 2584 fully side overlapping quantum well 2582 and particle 2586.

A diagram illustrating an example quantum structure with partial center well to gate overlap is shown in FIG. 60C. The structure, generally referenced 2570, comprises a control gate 2574 partially center overlapping quantum well 2572 and possible particle 2576.

A diagram illustrating an example quantum structure with partial side well to gate overlap is shown in FIG. 60D. The structure, generally referenced 2590, comprises a control gate 2594 partially side overlapping quantum well 2592 and particle 2596.

Note that in the above structures, the control gate has a much smaller size compared to the well in order to reduce the capacitance of the structure and increase the Coulomb blockade voltage.

In the structures of the present invention described herein, the tunneling of the quantum particles occurs from the left well to the right well and then from the right well to the left well, then continually repeating. If the tunneling control signal maintains the tunneling barrier low for a longer time interval, a Rabi (occupancy) oscillation is established between the two quantum wells. The Rabi oscillation stops when the tunneling barrier is raised by the potential applied to the control terminal. A diagram illustrating an example double qdot quantum structure using preferential tunneling on one side through thin oxide is shown in FIG. 61. The structure, generally referenced 2600, comprises thick oxide 2602 surrounding two quantum wells 2604 on three sides, a thin oxide layer 2606, and a control gate 2608. The double quantum qdot structure uses preferential tunneling on one side through thin oxide and quantum transport through the gate layer material 2608 as indicated by the arrows. Note that tunneling does not occur through the thick oxide layers.

A top view of several example embodiments of double qdot quantum structures using preferential tunneling on one side through thin oxide and a quantum transport through the gate layer will now be presented. A diagram illustrating a first example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer is shown in FIG. 62A. The structure, generally referenced 2610, comprises a control gate 2614 full center overlapping quantum wells 2612 and a possible quantum particle 2616.

A diagram illustrating a second example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer is shown in FIG. 62B. The structure, generally referenced 2620, comprises a control gate 2624 partial center overlapping quantum wells 2622 and particle 2626.

A diagram illustrating a third example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer is shown in FIG. 62C. The structure, generally referenced 2630, comprises a control gate 2634 full side overlapping quantum wells 2632 and particle 2636.

A diagram illustrating a fourth example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer is shown in FIG. 62D. The structure, generally referenced 2640, comprises a control gate 2644 partial side overlapping quantum wells 2642 and particle 2646.

Note that the quantum wells can be arranged side-by-side, one on top of the other or in diagonal fashion. A diagram illustrating a fifth example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer is shown in FIG. 62E. The structure, generally referenced 2650, comprises a control gate 2654 partial side overlapping quantum wells 2652 arranged in diagonal orientation and particle 2656.

A diagram illustrating a sixth example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer is shown in FIG. 62F. The structure, generally referenced 2660, comprises control gate material 2664 partial corner overlapping quantum wells 2662 arranged in diagonal orientation and particle 2666.

In another embodiment, the tunneling between the semiconductor well and the gate may be vertical when the gate is overlapping the well. Alternatively, the gate may not have any overlap with the well, but can be placed in very close proximity such that tunneling is still possible. A diagram illustrating a seventh example double qdot quantum structure with preferential tunneling one side through thin oxide and quantum transport through the gate layer arrangement is shown in FIG. 62G. The structure, generally referenced 2670, comprises a control gate structure arrangement 2674 with no physical overlap of the quantum wells 2672, and particle 2676. The wells are in close proximity to the gate forming very narrow apertures 2678 that allow preferential tunneling through a relatively thin oxide layer.

In order to maintain a quantum particle/quantum state in a semiconductor well, it is preferable that any leakage current from the structure be negligible. It is possible to implement semiconductor quantum structures in standard bulk processes that offer junction type isolation of the well. Making the leakage current through the isolation junctions negligible, however, is difficult. A diagram illustrating example preferential tunneling through thin oxide in a planar bulk semiconductor process with reverse biased junction isolation is shown in FIG. 63. The structure, generally referenced 2680, comprises substrate 2682, semiconductor layer other than oxide 2684, quantum well 2688, thin oxide layer 2686, and floating gate 2681. Here, leakage current 2683 exists through the reverse biased junction. Therefore, it is preferable for the isolation to be realized with actual oxide layers, e.g., silicon oxide, etc.

A diagram illustrating example preferential tunneling through thin oxide in a planar SOI semiconductor process with buried thick oxide and thick side trench oxide layers is shown in FIG. 64. The structure, generally referenced 2690, comprises substrate 2692 (e.g., semiconductor, insulator, etc.), buried thick oxide (BOX) layer 2694, quantum well 2693, thick side trench oxide layer 2696, thin oxide layer 2691, and floating gate 2698 partially overlapping the well (full overlap is also possible). In this case, the leakage currents through the thick oxide layers are negligible and the single leakage current is the one through the thin oxide layer which is controlled by the control terminal, as indicated by the arrow.

A diagram illustrating an example double quantum dot semiconductor quantum structure using planar SOI process with preferential tunneling between the well and gate is shown in FIG. 65. The structure, generally referenced 2700, comprises substrate 2702 (e.g., semiconductor, insulator, etc.), buried thick oxide (BOX) layer 2704, quantum wells 2701, thick side trench oxide layer 2706, thin oxide layer 2708, and control gate material 2703 partially overlapping both wells. The tunneling path through the thin oxide layer and control gate is indicated by the arrows.

Note that the substrate of the structures may comprise the semiconductor substrate usually used in semiconductor processes, or it may comprise an insulator that is obtained through a semiconductor substrate elimination and replacement process. The drawback of a semiconductor process is that dopants from the substrate may interact with the quantum particles. It is thus preferable to have a low doped/high resistivity substrate which minimizes such parasitic substrate interactions. High resistivity substrates, however, are not always available. If only moderately doped substrates are available, a substrate replacement process may be used.

To construct more complex semiconductor structures, two or more quantum particles/states are allowed to interact (i.e. entangle). This can be achieved in semiconductor structures having a larger number of qdots (i.e. semiconductor wells). For example, a four qdot structure brings two quantum particles in close proximity to each other to interact. A diagram illustrating example pair of double quantum dot semiconductor quantum structures using preferential tunneling and placed in close proximity to enable interaction between them is shown in FIG. 66. The structure, generally referenced 2710, comprises substrate 2712 (e.g., semiconductor, insulator, etc.), buried thick oxide (BOX) layer 2714, quantum wells 2713, thick side trench oxide layer 2716, thin oxide layer 2711, and gates 2718 partially overlapping the wells. The side trench isolation oxide is wide enough that no significant leakage current exists between the two quantum wells that interact. Thus, only the particle-to-particle quantum interaction impact their quantum states. Note, however, that there may be parasitic interactions from other structures.

Thus far, structures having only a single preferential tunneling direction have been presented. In general, more than one preferential tunneling direction may exist in a structure. A diagram illustrating an example semiconductor quantum structure using preferential tunneling on two sides with front and back gates and full gate to well overlap is shown in FIG. 67A. The structure, generally referenced 2720, comprises quantum well 2728, thick oxide 2722, thin oxide layer 2723, front control gate 2724, thin oxide layer 2726, and back control gate 2721. Both front and back control gates fully overlap the quantum well.

A diagram illustrating an example semiconductor quantum structure using preferential tunneling on two sides with front and back gates and partial gate to well overlap is shown in FIG. 67B. The structure, generally referenced 2730, comprises quantum well 2738, thick oxide 2732, thin oxide layer 2733, front control gate 2734, thin oxide layer 2736, and back control gate 2731. Both front and back control gates partially overlap the quantum well.

Both structures 2720, 2730 use two preferential tunneling sides with a front control gate with thin oxide layer and a back control gate with thin oxide layer: In one embodiment, the front gate oxide is a thin oxide layer. In older processes, the back oxide layer (e.g., the BOX layer that isolates the quantum well from the substrate) was relatively thick. In more recent advanced SOI processes, the BOX oxide layer is relatively thin. Also, some modern SOI processes offer back control gates realized with the doped layer situated below the BOX oxide. Thus, tunneling can be achieved to back control gates as well.

In another embodiment, the back control gate impacts the tunneling between the well and the front gate. The potential applied to the back control gate may be varied with external signals resulting in control of the main tunneling of the front control gate.

The semiconductor quantum structures using preferential tunneling direction described supra can also be implemented in 3D processes. The implementation depends on the features and capabilities of the particular process used. A diagram illustrating an example 3D semiconductor quantum structure (e.g. FinFET process) with three preferential tunneling directions around a fin based quantum well is shown in FIG. 67C. The structure, generally referenced 2740, comprises a substrate (not shown) which can be bulk, SOI or insulating, etc., thick oxide layer 2742, 3D semiconductor fin quantum well 2748, possible quantum particle 2741, thin oxide 2746, and control gate 2744. In this embodiment, the thin oxide layer between the 3D semiconductor fin and the gate has the same thickness on all three directions.

More complex 3D semiconductor quantum structures can be implemented using multiple fin layers. A diagram illustrating an example double quantum dot 3D semiconductor quantum structure with three preferential tunneling directions around a fin based quantum well is shown in FIG. 67D. The structure, generally referenced 2750, comprises substrate 2752 which may comprise bulk, SOI or insulating, etc., thick oxide layer 2754, 3D semiconductor fin quantum well 2762, particle 2764, thin oxide 2758, and control gate 2760. In this example, quantum transport occurs from quantum fin well #1 through the control gate layer to quantum fin well #2.

In one embodiment, the 3D process realizes different gate oxide thicknesses on the sides and on the top. For example, the thickness on the top is made much smaller than the thickness on the side walls. This effectively gives the 3D structure a single preferential tunneling direction, since the tunneling will occur primarily through the thin top oxide layer. A diagram illustrating an example 3D semiconductor quantum structure with preferential tunneling on one side only through this oxide is shown in FIG. 67E. The structure, generally referenced 2770, comprises a substrate (not shown) which can be bulk, SOI or insulating, etc., thick oxide layer 2772, 3D semiconductor fin quantum well 2780, particle 2782, thin oxide 2778, thick side wall oxide 2776, and control gate 2774. In this example, the tunneling occurs through the thin top oxide. The side oxide layers are thicker than the top thus making tunneling through them exponentially weaker.

Different shapes may be used for the wells and the gates in practical semiconductor processes. Although square and rectangular shapes are most often used, some processes allow 45 degree angle lines thereby enabling other polygonal shapes. In addition, some semiconductor processes allow circular shapes. In one embodiment, a circular shape can be implemented using a high order polygonal contour. In the case of 3D semiconductor processes, a quantum well may be realized by a combination of a planar well and a 3D fin structure. A diagram illustrating a first example semiconductor quantum structure using a composed shape to realize a double quantum dot with preferential tunneling is shown in FIG. 68A. The generic semiconductor quantum structure, generally referenced 2790, comprises a composed shape for the quantum wells 2792 (e.g., well and fin, or wide well to narrow well) to realize a double qdot with preferential tunneling direction. The floating gate 2794 that overlaps the two fins realizes the tunneling and transport path. A corresponding potential plot 2798 illustrates the controlled tunnel barrier that enables quantum transport of a particle between quantum well #1 and quantum well #2.

A diagram illustrating a second example semiconductor quantum structure using a rectangular shape to realize a double quantum dot with preferential tunneling is shown in FIG. 68B. The generic semiconductor quantum structure, generally referenced 2800, comprises a rectangular shape (available in all semiconductor processes) for the quantum wells 2802 (e.g., well and fin, or wide well to narrow well) to realize a double qdot with preferential tunneling direction. The gate 2804 that overlaps the two fins realizes the tunneling and transport path. A corresponding potential plot 2808 illustrates the controlled tunnel barrier that enables quantum transport of a particle between quantum well #1 and quantum well #2.

The tunneling based operation of the semiconductor quantum structures of the present invention can be illustrated using the potential plot along the quantum operation path (i.e. the chord line). A high barrier blocks tunneling (i.e. reduces its probability), while a lower barrier level allows tunneling (i.e. increases its probability). A diagram illustrating an example potential distribution along the chord line of operation in a two path, three quantum dot semiconductor quantum structure with large tunneling barrier and tunneling time is shown in FIG. 69A. As shown in the plots 2810, 2812, the tunneling barriers are high, thus preventing (i.e. making negligible) tunneling of the particle in the lower left qdot. A unidimensional potential plot is shown which is appropriate for aperture tunneling semiconductor devices where the particles follow a narrow aperture path and the probability for the more remote path is very low (i.e. negligible).

When the appropriate potential on the control gate causes lowering of a given tunneling barrier, the particle situated on one side of the barrier will tunnel to the other side. The duration the barrier is kept low determines the probability that a particle is present in the left or in the right quantum well. A diagram illustrating an example potential distribution along the chord line of operation in a two path, three quantum dot semiconductor quantum structure with lower tunneling barrier is shown in FIG. 69B. As shown in the plots 2814, 2816, when one of the tunnel barriers is lowered (in the lower path), the particle is permited to tunnel between two quantum dots.

As the tunneling barrier is kept low, the particle tunnels back and forth from one side of the barrier to the other, establishing a Rabi oscillation. When the potential on the control gate causes the tunneling barrier to rise, the tunneling effect is again blocked (i.e. the probability of tunneling becomes negligible). Depending on the exact time the barrier is raised, the particle may be blocked in the left well, the right well, or be split in a certain proportion between the two wells. A diagram illustrating an example potential distribution along the chord line of operation in a two path, three quantum dot semiconductor quantum structure with the barrier raised after the particle has tunneled is shown in FIG. 69C. As shown in plots 2818, 2820, a second particle is loaded in the upper quantum path, tunneling barriers are high and the first particle in the lower quantum path was split between two quantum wells.

Having the first particle split in a given proportion (i.e. create a specific quantum state) and lowering the tunneling barrier of the second particle in the upper path, interaction between the two particles is thereby enabled. This results in a particular split of the second particle. As a result of the interaction and the split of the second particle, the potential in the second well changes. A diagram illustrating an example potential distribution along the chord line of operation in a two path, three quantum dot semiconductor quantum structure where the particles are allowed to interact and tunnel is shown in FIG. 69D. As shown in the plots 2822, 2824, the two particles/quantum states are allowed to interact by lowering at least one tunneling barrier in the upper quantum path.

An example of semiconductor quantum well using preferential direction tunneling through thin oxide layer and having a single particle injection structure is shown in FIG. 35. As described supra, the single electron injection circuit 1102 takes one electron from the classic well on the left and injects it into well in accordance with the control gate signal.

Some commercially available semiconductor processes may allow different types of geometric shapes to be used for the various layers in fabricating a semiconductor quantum structure. FIG. 7A through 7S, described supra, provide several examples of shapes that can be used for the layers of a semiconductor quantum structure.

Further, there are several ways to implement the control terminal in a planar semiconductor process. In one embodiment, the control terminal is electrically floating or it may be electrically driven. FIG. 49B, described supra, shows the cross section of a semiconductor quantum structure 2250 using preferential tunneling direction showing the floating control terminal layer 2262 in proximity to the gate 2260. The floating control terminal may comprise a metal layer on top or on the side, another gate layer, or another well placed in close proximity to the gate. Note that the closest placed control layer provides the most effective action. Note also that in this embodiment, the gate layer functions as both the tunneling path and the transport path for the quantum particle.

A diagram illustrating a cross section of an example semiconductor quantum structure using preferential tunneling with a metal control terminal layer in proximity of the gate is shown in FIG. 70. The quantum structure, generally referenced 2830, comprises a substrate 2832, oxide layer 2834, well 2836 for horizontal tunneling, thin oxide 2844, polysilicon gate 2838, optional electrical contact 2846, local depleted region 2842, and metal tunneling control 2840. The structure uses preferential tunneling direction with the electrically contacted control terminal layer in proximity to the gate. The control terminal may comprise a metal layer on top or on the side, another gate layer, or another well placed in close proximity to the gate. Note that the closest placed control layer provides the most effective action.

The substrate of the structure is important to provide mechanical strength to the structure. Standard semiconductor processes provide semiconductor substrates for the structure. More advanced semiconductor processes can remove the semiconductor substrate and replace it with another material (insulator) or keep it empty.

A diagram illustrating use of a buried oxide layer to isolate quantum wells from the substrate in an SOI process based quantum structure with preferential tunneling to minimize parasitic interaction is shown in FIG. 71A. The structure, generally referenced 2840, comprises substrate 2842, BOX 2844, trench oxide (STI) 2846, wells 2852, particle 2854, thin oxide 2850, and gate 2848. In this embodiment, the buried oxide layer functions to isolate the quantum wells from the substrate.

A diagram illustrating substrate elimination in an SOI process based quantum structure with preferential tunneling to minimize parasitic interaction is shown in FIG. 71B. The structure, generally referenced 2860, comprises BOX 2862, trench oxide (STI) 2864, wells 2866, particle 2872, thin oxide 2870, and gate 2868. In this embodiment, the substrate is eliminated in an SOI process using any suitable technique, e.g., etching, polishing, etc. The quantum structure has preferential tunneling direction to minimize substrate parasitic interaction (i.e. decoherence).

In another embodiment, the substrate may be partially eliminated, while in other cases it is completely eliminated and replaced with another material that has lower parasitic quantum interaction (e.g., an insulator). A diagram illustrating substrate thinning in an SOI process based quantum structure with preferential tunneling to minimize parasitic interaction is shown in FIG. 71C. The structure, generally referenced 2880, comprises a partially eliminated substrate 2882, BOX 2884, trench oxide (STI) 2886, wells 2894, particle 2892, thin oxide 2890, and gate 2888. In this embodiment, the substrate is partially eliminated in an SOI process using any suitable technique, e.g., etching, polishing, etc. The structure uses preferential direction of tunneling and thinning of the substrate to reduce substrate (i.e. parasitic) interactions.

A diagram illustrating substrate replacement with inert material in an SOI process based quantum structure with preferential tunneling to minimize parasitic interaction is shown in FIG. 71D. The structure, generally referenced 2900, comprises a substrate replacement 2902, BOX 2904, trench oxide (STI) 2906, wells 2908, particle 2914, thin oxide 2912, and control gate material 2910. In this embodiment, the substrate is replaced with inert material that reduces substrate parasitic interaction.

Control of the tunneling effect is realized by imposing the potential on the control gate layer that plays the role of tunneling and transport path. FIG. 51B, described supra, shows the potential imposing on the floating gate 2396 from a metal layer 2392 on the top or on the side.

FIG. 51A, also described supra, provides an alternative mechanism of imposing the potential on the floating gate 2304 using an imposer well 2309, imposer gate 2302 or imposer metal 2298.

A diagram illustrating an example 3D semiconductor quantum structure using preferential tunneling direction and imposer metal to set the potential on the floating gate is shown in FIG. 72. The structure, generally referenced 2920, comprises substrate 2922, BOX 2924, semiconductor quantum fins 2932, particle 2930, thin oxide layer 2934, and control gate layer 2936.

FIG. 51C described supra, an illustrative 3D semiconductor quantum structure 2310 using preferential tunneling direction and different ways to impose the potential on the floating gate using imposer-fin 2329, imposer-gate 2318, and imposer-metal 2316.

A diagram illustrating a top view of an example semiconductor quantum structure using preferential tunneling direction implemented in a planar semiconductor process using rectangular well and gate shapes and full gate-to-well overlap is shown in FIG. 73A. The structure, generally referenced 2940, comprises a gate 2944 fully overlapping two quantum wells 2942 to enable tunneling 2946 through the oxide layer (not shown).

FIG. 46B, described supra, shows an alternative embodiment of a semiconductor quantum structure 2100 using preferential tunneling direction implemented in a planar semiconductor process using rectangular wells 2102, 2104 and control gate shapes, and partial gate-to-well overlap, i.e. half full edge overlap.

A diagram illustrating an example semiconductor quantum structure using preferential tunneling direction implemented in a planar semiconductor process using rectangular well and gate shapes and partial gate-to-well overlap is shown in FIG. 73B. The structure, generally referenced 2950, comprises a gate 2954 partially corner overlapping two quantum wells 2952 to enable tunneling 2956 through the thin oxide layer (not shown).

FIG. 40A, described supra, is an example of a double qdot semiconductor quantum structure 1430 with preferential tunneling direction implemented in a planar semiconductor process with corner overlap. Similarly, FIG. 40C, also described supra, is an example of a double qdot semiconductor quantum structure 1440 with preferential tunneling direction implemented in a 3D semiconductor process.

Those skilled in the art will recognize that the boundaries between logic and circuit blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality.

Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermediary components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first,” “second,” etc. are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. As numerous modifications and changes will readily occur to those skilled in the art, it is intended that the invention not be limited to the limited number of embodiments described herein. Accordingly, it will be appreciated that all suitable variations, modifications and equivalents may be resorted to, falling within the spirit and scope of the present invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. 

What is claimed is:
 1. A quantum structure, comprising: a substrate; isolation material fabricated on said substrate; a first quantum well and a second quantum well surrounded partially or completely at least on two sides by said isolation material; a quantum transport path fabricated on said isolation layer overlaying said first quantum well and said second quantum well, and operative to provide conduction transport of a quantum particle therebetween; a first preferential tunneling path between said first quantum well and said quantum transport path; and a second preferential tunneling path between said second quantum well and said quantum transport path.
 2. The quantum structure according to claim 1, wherein an electric field applied to said quantum transport path is operative to control a tunneling barrier of said quantum particle through said first preferential tunneling path and said second preferential tunneling path.
 3. The quantum structure according to claim 1, wherein said first quantum well, said second quantum well, said isolation material, and said quantum transport path are constructed using a planar process configuration.
 4. The quantum structure according to claim 1, wherein said first quantum well, said second quantum well, said isolation material, and said quantum transport path are constructed using a 3D process configuration.
 5. The quantum structure according to claim 1, wherein said substrate is selected from a group comprising a semiconductor, silicon on insulator (SOI), and insulating substrate replacement.
 6. The quantum structure according to claim 1, wherein said quantum transport path is selected from a group comprising polysilicon, metal, oxide, and quantum well.
 7. The quantum structure according to claim 1, wherein said isolation material is selected from a group comprising buried oxide (BOX), and shallow trench isolation (STI).
 8. The quantum structure according to claim 1, wherein said first quantum well and said second quantum well material are selected from a group comprising undoped silicon, and low doped silicon.
 9. The quantum structure according to claim 1, wherein said first preferential tunneling path and said second preferential tunneling path are sufficiently thin to allow quantum tunneling of said quantum particle between said first quantum well, said second quantum well, and said quantum transport path.
 10. The quantum structure according to claim 1, wherein said quantum transport path is configured to either fully or partially overlay said first quantum well and said second quantum well to create a full or partial aperture thereby.
 11. A quantum structure, comprising: a substrate; isolation material fabricated on said substrate; a semiconductor well surrounded partially or completely at least on two sides by said isolation material; a back gate layer fabricated below said semiconductor well; a front gate layer fabricated above said semiconductor well; a first preferential tunneling path between said semiconductor well and said back gate; and a second preferential tunneling path between said semiconductor well and said front gate.
 12. The quantum structure according to claim 11, wherein said isolation material is selected from a group comprising buried oxide (BOX), and shallow trench isolation (STI).
 13. The quantum structure according to claim 11, wherein said semiconductor well material is selected from a group comprising undoped silicon, and low doped silicon.
 14. The quantum structure according to claim 11, wherein said first preferential tunneling path and said second preferential tunneling path is sufficiently thin to allow quantum tunneling of said quantum particle between said semiconductor well and said back gate and said front gate, respectively.
 15. The quantum structure according to claim 11, wherein said back gate and said front gate are configured to either fully or partially overlay said semiconductor well to create a full or partial aperture thereby.
 16. A method of fabricating a quantum structure, comprising: providing a substrate material; fabricating isolation material on said substrate; fabricating a first quantum well and a second quantum well surrounded partially or completely on at least two sides by said isolation material; fabricating a quantum transport path on said isolation material overlaying said first quantum well and said second quantum well, and operative to provide conduction transport of a quantum particle between said first quantum well to said second quantum well; forming a first preferential tunneling path between said first quantum well and said quantum transport path; and forming a second preferential tunneling path between said second quantum well and said quantum transport path.
 17. The method according to claim 16, further comprising ac coupling a voltage potential to said quantum transport path to control a tunneling barrier of a quantum particle through said first preferential tunneling path, said quantum transport path, and said second preferential tunneling path.
 18. The method according to claim 16, wherein said first preferential tunneling path and said second preferential tunneling path are sufficiently thin to allow quantum tunneling of said quantum particle between said first quantum well, said second quantum well, and said quantum transport path.
 19. The method according to claim 16, wherein said quantum transport path material is selected from a group comprising polysilicon, metal, oxide, and quantum well.
 20. The method according to claim 16, wherein said isolation material is selected from a group comprising buried oxide (BOX), and shallow trench isolation (STI).
 21. The method according to claim 16, wherein said first quantum well, said second quantum well, said isolation material, and said quantum transport path are constructed using a planar semiconductor process configuration.
 22. The method according to claim 16, wherein said first quantum well, said second quantum well, said isolation material, and said quantum transport path are constructed using a 3D semiconductor process configuration. 